[Paper Review] Automated Space/Time Scaling of Streaming Task Graph

Hossein Omidian, Guy Lemieux|arXiv (Cornell University)|Jun 12, 2016

Parallel Computing and Optimization Techniques7 references3 citations

TL;DR

This paper presents an automated high-level synthesis (HLS) tool for streaming task graphs (STG) targeting massively parallel processor arrays (MPPA) on FPGAs, enabling dynamic area-throughput trade-offs through node replication, splitting, and combining. It uses both integer linear programming (ILP) and a novel heuristic to optimize space/time scaling, with results showing the heuristic outperforms ILP by finding superior design points not accessible via formal methods.

ABSTRACT

In this paper, we describe a high-level synthesis (HLS) tool that automatically allows area/throughput trade-offs for implementing streaming task graphs (STG). Our tool targets a massively parallel processor array (MPPA) architecture, very similar to the Ambric MPPA chip architecture, which is to be implemented as an FPGA overlay. Similar to Ambric tools, our HLS tool accepts a STG as input written in a subset of Java and a structural language in the style of a Kahn Processing Network (KPN). Unlike the Ambric tools, our HLS tool analyzes the parallelism internal to each Java "node" and evaluates the throughput and area of several possible implementations. It then analyzes the full graph for bottlenecks or excess compute capacity, selects an implementation for each node, and even considers replicating or splitting nodes while either minimizing area (for a fixed throughput target), or maximizing throughput (for a fixed area target). In addition to traditional node selection and replication methods used in prior work, we have uniquely implemented node combining and splitting to find a better area/throughput trade-off. We present two optimization approaches, a formal ILP formulation and a heuristic solution. Results show that the heuristic is more flexible and can find design points not available to the ILP, thereby achieving superior results.

Motivation & Objective

• To enable automated, high-level synthesis of streaming task graphs (STG) for MPPA architectures on FPGAs.
• To support dynamic area/throughput trade-offs through runtime optimization of task graph components.
• To improve upon prior work by introducing node combining and splitting in addition to replication and selection.
• To develop both formal (ILP) and heuristic optimization strategies for scalable design space exploration.
• To demonstrate superior design point discovery using the heuristic over ILP-based approaches.

Proposed method

• The tool accepts STGs described in a subset of Java and a Kahn Process Network (KPN)-style structural language.
• It analyzes intrinsic parallelism within each STG node to evaluate multiple implementation options for throughput and area.
• It performs system-level analysis to detect bottlenecks or underutilized compute capacity across the graph.
• It applies node replication, splitting, and combining to explore diverse area-throughput trade-offs.
• It formulates the optimization as an integer linear program (ILP) for formal solution and implements a heuristic for broader exploration.
• The heuristic enables discovery of non-ILP-feasible design points, enhancing flexibility and performance.

Experimental results

Research questions

• RQ1 Can automated HLS tools effectively explore the design space of streaming task graphs for MPPA architectures?
• RQ2 How do node combining and splitting improve area-throughput trade-offs compared to traditional replication and selection?
• RQ3 What is the relative performance of heuristic vs. ILP-based optimization in finding optimal design points?
• RQ4 Can the heuristic approach discover superior design points not reachable via formal ILP formulation?
• RQ5 To what extent does the proposed method improve throughput under fixed area constraints or reduce area under fixed throughput targets?

Key findings

• The heuristic optimization approach discovers design points not accessible to the ILP formulation, demonstrating greater flexibility in design space exploration.
• The heuristic achieves superior area-throughput trade-offs compared to the ILP, particularly in complex, irregular task graphs.
• Node combining and splitting techniques significantly expand the design space, enabling better utilization of hardware resources.
• The tool successfully supports both area-minimization (fixed throughput) and throughput-maximization (fixed area) design objectives.
• The results validate the effectiveness of high-level synthesis with runtime-aware optimization for streaming workloads on FPGA-based MPPA architectures.