[Paper Review] Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics

Stephanie Soldavini, Karl F. A. Friebel+4 more|arXiv (Cornell University)|Mar 21, 2022

Parallel Computing and Optimization TechniquesComputer Science62 references9 citations

TL;DR

This paper presents an automated toolchain that compiles domain-specific language (DSL) descriptions of tensor operations in computational fluid dynamics into optimized high-bandwidth memory (HBM)-equiped FPGA accelerators. Using an MLIR-based compiler and HLS flow, it generates custom hardware with efficient data movement, achieving up to 103 GFLOPS and 25× higher energy efficiency than expert-crafted CPU implementations on a Xilinx Alveo U280.

ABSTRACT

Numerical simulations can help solve complex problems. Most of these algorithms are massively parallel and thus good candidates for FPGA acceleration thanks to spatial parallelism. Modern FPGA devices can leverage high-bandwidth memory technologies, but when applications are memory-bound designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. This development process requires hardware design skills that are uncommon in domain-specific experts. In this paper, we propose an automated tool flow from a domain-specific language (DSL) for tensor expressions to generate massively-parallel accelerators on HBM-equipped FPGAs. Designers can use this flow to integrate and evaluate various compiler or hardware optimizations. We use computational fluid dynamics (CFD) as a paradigmatic example. Our flow starts from the high-level specification of tensor operations and combines an MLIR-based compiler with an in-house hardware generation flow to generate systems with parallel accelerators and a specialized memory architecture that moves data efficiently, aiming at fully exploiting the available CPU-FPGA bandwidth. We simulated applications with millions of elements, achieving up to 103 GFLOPS with one compute unit and custom precision when targeting a Xilinx Alveo U280. Our FPGA implementation is up to 25x more energy-efficient than expert-crafted Intel CPU implementations.

Motivation & Objective

• Address the productivity gap between domain experts (e.g., CFD scientists) and low-level FPGA hardware design.
• Overcome performance bottlenecks in memory-bound HBM-equipped FPGA accelerators due to inefficient data movement and limited hardware expertise.
• Enable non-FPGA experts to explore and evaluate multiple hardware and compiler optimizations through a high-level DSL.
• Automate the generation of HBM-optimized system architectures with parallel accelerators and efficient on-chip memory hierarchies.
• Achieve high performance and energy efficiency in HPC workloads like CFD by leveraging MLIR and commercial HLS tools.

Proposed method

• Use a domain-specific language (DSL) to express tensor operations in CFD, such as the Inverse Helmholtz operator, in a platform-agnostic way.
• Employ an MLIR-based compiler to lower the DSL specification while preserving semantics and generating HLS-ready C++ code.
• Integrate an in-house hardware generation flow that uses commercial HLS tools to synthesize compute units and memory architectures.
• Apply key optimizations including Double Buffering, Bus Optimization (Parallel), and Dataflow partitioning to maximize HBM bandwidth utilization.
• Design a custom memory architecture around compute units to minimize CPU-FPGA data transfer latency and maximize data throughput.
• Target the Xilinx Alveo U280 FPGA with HBM2, supporting up to 460 GB/s bandwidth, and evaluate with 3D tensor kernels.

Experimental results

Research questions

• RQ1 Can a DSL-to-bitstream flow automate the generation of HBM-optimized FPGA accelerators for memory-bound CFD kernels?
• RQ2 To what extent can MLIR-based compilation and HLS automation improve productivity and performance for non-FPGA experts in HPC domains?
• RQ3 How effective are hardware and compiler optimizations—such as dataflow partitioning and double buffering—in exploiting HBM bandwidth on FPGAs?
• RQ4 What performance and energy efficiency gains can be achieved compared to highly optimized CPU implementations?
• RQ5 How do data format (e.g., 32-bit fixed-point vs. double-precision) and polynomial degree impact resource usage and performance?

Key findings

• The optimized FPGA implementation of the Inverse Helmholtz kernel achieved up to 103 GFLOPS with one compute unit and custom-precision data types on a Xilinx Alveo U280.
• The FPGA accelerator achieved up to 160.2× speedup over the AMD EPYC 7282 CPU and 2.7× speedup over highly optimized Intel CPU code.
• The most energy-efficient FPGA design (32-bit fixed-point, p=11, 1 CU) delivered 24.5× higher energy efficiency (GFLOPS/W) than the corresponding Intel CPU implementation.
• The fully optimized FPGA kernels achieved 36.4× to 160.2× speedup over the AMD EPYC 7282 CPU, demonstrating significant performance gains.
• The MLIR-based compiler enabled rapid prototyping and composition, with improved diagnostics, stability, and modularity compared to prior custom IRs.
• The framework allows non-FPGA experts to explore multiple optimization strategies—such as dataflow partitioning and memory buffering—without low-level hardware expertise.