[Paper Review] AutoSoC: Automating Algorithm-SOC Co-design for Aerial Robots

Srivatsan Krishnan, Thierry Tambe+2 more|arXiv (Cornell University)|Sep 13, 2021

Robotics and Sensor-Based Localization28 references4 citations

TL;DR

AutoSoC is a framework for automated algorithm-SOC co-design in aerial robots, enabling end-to-end learning-based navigation with hardware accelerator generation. It achieves 91% success rate in cluttered environments and generates accelerator candidates with latency from 4.8–60.2 μs and power consumption from 0.142–1.09 W, optimizing for performance, area, and energy trade-offs.

ABSTRACT

Aerial autonomous machines (Drones) has a plethora of promising applications and use cases. While the popularity of these autonomous machines continues to grow, there are many challenges, such as endurance and agility, that could hinder the practical deployment of these machines. The closed-loop control frequency must be high to achieve high agility. However, given the resource-constrained nature of the aerial robot, achieving high control loop frequency is hugely challenging and requires careful co-design of algorithm and onboard computer. Such an effort requires infrastructures that bridge various domains, namely robotics, machine learning, and system architecture design. To that end, we present AutoSoC, a framework for co-designing algorithms as well as hardware accelerator systems for end-to-end learning-based aerial autonomous machines. We demonstrate the efficacy of the framework by training an obstacle avoidance algorithm for aerial robots to navigate in a densely cluttered environment. For the best performing algorithm, our framework generates various accelerator design candidates with varying performance, area, and power consumption. The framework also runs the ASIC flow of place and route and generates a layout of the floor-planed accelerator, which can be used to tape-out the final hardware chip.

Motivation & Objective

• To address the challenge of low flight endurance and limited agility in resource-constrained aerial robots due to high compute latency in control loops.
• To enable efficient deployment of end-to-end (E2E) deep reinforcement learning models for autonomous navigation in cluttered environments.
• To co-optimize neural network architecture and hardware accelerator design for performance, power, and area efficiency.
• To automate the generation of ASIC-qualitative accelerator layouts via place-and-route flows for tape-out-ready designs.

Proposed method

• The framework uses a curriculum learning-based DQN agent to train an end-to-end policy for obstacle avoidance in a simulated, densely cluttered environment.
• It co-designs the E2E model and hardware accelerator by exploring a multi-dimensional design space including PE count, MAC lane width, and precision (8-bit/4-bit).
• A custom accelerator template, FlexACL, is generated with configurable parallelism and precision to support performance, power, and area trade-offs.
• The framework synthesizes accelerator candidates using high-level synthesis (HLS) and evaluates them using a 16nm standard cell library at 300MHz.
• Post-HLS Verilog RTL is used to estimate performance, power, and area, and the final design undergoes place-and-route to produce a tape-out-ready floorplan.

Experimental results

Research questions

• RQ1 Can automated co-design of E2E learning models and hardware accelerators improve control loop frequency and reduce energy consumption in aerial robots?
• RQ2 How can a unified framework efficiently explore the trade-offs between performance, power, and area in accelerator design for robotic control?
• RQ3 To what extent can end-to-end learning achieve high success rates in complex, cluttered navigation tasks while remaining deployable on resource-constrained platforms?
• RQ4 What is the impact of varying precision (8-bit vs 4-bit) and parallelism (PE count, MAC lanes) on accelerator efficiency for robotic control workloads?

Key findings

• The E2E DQN model achieved a 91% success rate in navigating a densely cluttered environment over 100 test trajectories.
• The trained model achieved a cumulative reward plateau at 1000 after approximately 2000 training epochs, indicating stable policy convergence.
• The generated FlexACL accelerator candidates achieved a latency range of 4.8 μs to 60.2 μs, with power consumption between 0.142 W and 1.09 W.
• The 8PEs-16MAC lanes configuration represented the optimal compromise in performance, power, and area, located at the knee of the efficiency curves.
• The 4PEs-16MAC lanes variant achieved the lowest power and area, while the 32PEs-16MAC lanes variant delivered the shortest latency but highest resource cost.
• The framework successfully generated a place-and-routed layout for a 4PE FlexACL accelerator, demonstrating readiness for ASIC tape-out.