[Paper Review] Balanced Modulation for Nonvolatile Memories

Hongchao Zhou, Anxiao Jiang+2 more|arXiv (Cornell University)|Sep 4, 2012

Advanced Memory and Neural Computing21 references17 citations

TL;DR

This paper proposes balanced modulation for nonvolatile memories, a practical writing/reading scheme that minimizes asymmetric errors by encoding data using balanced error-correcting codes and dynamically adjusting reading thresholds to maintain balanced codewords. It introduces efficient constructions of balanced LDPC codes with low redundancy and high performance, significantly reducing bit error rates without requiring prior knowledge of cell-level distributions.

ABSTRACT

This paper presents a practical writing/reading scheme in nonvolatile memories, called balanced modulation, for minimizing the asymmetric component of errors. The main idea is to encode data using a balanced error-correcting code. When reading information from a block, it adjusts the reading threshold such that the resulting word is also balanced or approximately balanced. Balanced modulation has suboptimal performance for any cell-level distribution and it can be easily implemented in the current systems of nonvolatile memories. Furthermore, we studied the construction of balanced error-correcting codes, in particular, balanced LDPC codes. It has very efficient encoding and decoding algorithms, and it is more efficient than prior construction of balanced error-correcting codes.

Motivation & Objective

• To address the asymmetric error problem in nonvolatile memories caused by cell-level drifts, such as charge leakage in flash or crystallization in PCM.
• To design a practical writing/reading scheme that minimizes asymmetric errors without relying on fixed or assumed cell-level distributions.
• To develop efficient constructions of balanced error-correcting codes, particularly balanced LDPC codes, for use in multi-level cell memories.
• To enable dynamic threshold adjustment during read operations such that the resulting read word is balanced or approximately balanced.
• To reduce redundancy in balanced code construction while maintaining strong error-correcting capability and computational efficiency.

Proposed method

• Encoding data using balanced error-correcting codes, where each codeword has an equal number of 1s and 0s (or balanced symbols in multi-level case).
• Dynamically adjusting the reading threshold such that the read word is balanced or approximately balanced, minimizing asymmetric error components.
• Using a generalized Knuth-style algorithm to construct balanced codes over nonbinary alphabets by grouping levels and iteratively balancing symbol counts across groups.
• Applying a prefix-based scheme to store the index of the balancing shift, enabling decoding by reversing the encoding transformation.
• Designing balanced LDPC codes with efficient encoding and decoding algorithms that outperform prior constructions in terms of redundancy and performance.
• Integrating parity-check bits into partial-balanced codes to support error correction in multi-level cell (MLC) systems.

Experimental results

Research questions

• RQ1 Can a practical writing/reading scheme be designed for nonvolatile memories that minimizes asymmetric errors caused by cell-level drifts without requiring knowledge of the underlying voltage or resistance distributions?
• RQ2 How can balanced codes be efficiently constructed for nonbinary alphabets to support multi-level cell memories with minimal redundancy?
• RQ3 What is the theoretical and practical performance gain of using dynamic reading thresholds based on balanced codewords compared to fixed thresholds?
• RQ4 How can balanced LDPC codes be designed with low encoding/decoding complexity and high error-correcting capability?
• RQ5 What is the trade-off between redundancy and code efficiency in constructing balanced codes for nonbinary alphabets?

Key findings

• Balanced modulation significantly reduces bit error rates by minimizing asymmetric errors through dynamic threshold adjustment based on balanced codewords.
• The proposed method achieves suboptimal performance for any cell-level distribution, making it robust across diverse memory conditions.
• Balanced LDPC codes were constructed with very efficient encoding and decoding algorithms, outperforming prior constructions in both speed and redundancy.
• For alphabet size q=2 to 10, the redundancy of the proposed balanced code construction is at most 8.95 times higher than that of ideal full balanced codes, with the ratio increasing slowly with q.
• The method requires only O(log m) additional bits for storing the balancing index when m is large, enabling practical implementation with low overhead.
• Theoretical analysis proves the existence of a balancing shift index i such that the modified word achieves exact balance across predefined level groups, enabling systematic code construction.