[Paper Review] Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM

Nitin Rathi, Asmit De+2 more|arXiv (Cornell University)|Mar 20, 2016

Advanced Memory and Neural Computing5 references3 citations

TL;DR

This paper proposes cache bypassing and checkpointing techniques to defend against data security attacks on Spin-Transfer Torque RAM (STTRAM), which is vulnerable to environmental tampering due to its sensitivity to temperature and magnetic fields. By dynamically bypassing the last-level cache during attacks and restoring from periodic checkpoints, the system maintains error-free computation with only 8% average IPC degradation for a 50% attack duration and 2% energy overhead for full-duration attacks.

ABSTRACT

Spin-Transfer Torque RAM (STTRAM) is promising for cache applications. However, it brings new data security issues that were absent in volatile memory counterparts such as Static RAM (SRAM) and embedded Dynamic RAM (eDRAM). This is primarily due to the fundamental dependency of this memory technology on ambient parameters such as magnetic field and temperature that can be exploited to tamper with the stored data. In this paper we propose three techniques to enable error free computation without stalling the system, (a) stalling where the system is halted during attack; (b) cache bypass during gradually ramping attack where the last level cache (LLC) is bypassed and the upper level caches interact directly with the main memory; and, (c) checkpointing along with bypass during sudden attack where the processor states are saved periodically and the LLC is written back at regular intervals. During attack the system goes back to the last checkpoint and the computation continues with bypassed cache. We performed simulation for different duration and frequency of attack on SPLASH benchmark suite and the results show an average of 8% degradation in IPC for a one-time attack lasting for 50% of the execution time. The energy overhead is 2% for an attack lasting for the entire duration of execution.

Motivation & Objective

• Address the unique data security vulnerabilities in STTRAM, which are absent in volatile memories like SRAM and eDRAM.
• Mitigate risks posed by environmental factors such as temperature and magnetic fields that can alter stored data in STTRAM.
• Enable continuous, error-free computation during and after data security attacks without system stalling.
• Minimize performance and energy overheads while ensuring system resilience to both gradual and sudden attacks.

Proposed method

• Implement a stalling mechanism that halts the system during active attacks to prevent data corruption.
• Introduce cache bypassing during gradually increasing attacks, where the last-level cache (LLC) is bypassed and main memory is accessed directly by upper-level caches.
• Apply periodic checkpointing to save processor states at regular intervals to enable recovery after an attack.
• During sudden attacks, revert to the most recent checkpoint and continue execution with the LLC bypassed to maintain system integrity.
• Use a combination of hardware and software mechanisms to detect attack onset and trigger the appropriate defense strategy.
• Simulate the proposed techniques on the SPLASH benchmark suite under varying attack durations and frequencies to evaluate performance and energy trade-offs.

Experimental results

Research questions

• RQ1 How can STTRAM systems maintain data integrity under environmental attacks that exploit temperature and magnetic field dependencies?
• RQ2 What mechanisms can ensure continuous system operation during data security attacks without stalling execution?
• RQ3 What is the performance overhead (in IPC and energy) of defense mechanisms like checkpointing and cache bypassing under different attack scenarios?
• RQ4 How do the proposed techniques compare in effectiveness between gradual and sudden attack models?
• RQ5 Can periodic checkpointing and dynamic cache bypassing provide a viable trade-off between security, performance, and energy efficiency in STTRAM-based systems?

Key findings

• For a one-time attack lasting 50% of the execution time, the system experiences an average of 8% degradation in Instructions Per Cycle (IPC).
• When an attack persists for the entire execution duration, the energy overhead is measured at 2% due to checkpointing and bypassing mechanisms.
• The proposed techniques—cache bypassing and checkpointing—enable error-free computation without requiring system stalling during attacks.
• The combination of dynamic cache bypassing during gradual attacks and checkpoint-based recovery during sudden attacks ensures system resilience.
• Simulation results on the SPLASH benchmark suite confirm that the defense mechanisms are effective across diverse workloads and attack profiles.
• The approach maintains system availability and data integrity under realistic environmental threat models, offering a practical solution for STTRAM deployment.