[Paper Review] Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

Jason Blocklove, Siddharth Garg+2 more|arXiv (Cornell University)|May 22, 2023

Ferroelectric and Negative Capacitance Devices14 citations

TL;DR

This paper investigates using conversational LLMs (ChatGPT-4) as co-designers for HDL writing and hardware design, presenting a case study that produced a complete HDL for tapeout of an 8-bit processor and discusses benefits and limitations.

ABSTRACT

Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Given that these `conversational' LLMs perform best when used interactively, we perform a case study where a hardware engineer co-architects a novel 8-bit accumulator-based microprocessor architecture with the LLM according to real-world hardware constraints. We then sent the processor to tapeout in a Skywater 130nm shuttle, meaning that this `Chip-Chat' resulted in what we believe to be the world's first wholly-AI-written HDL for tapeout.

Motivation & Objective

• Motivate the use of conversational LLMs to assist in HDL development at the earliest stages of hardware design.
• Evaluate the potential of ChatGPT-4 as a co-architect in end-to-end HDL design for a real-world constraint such as Tiny Tapeout.
• Demonstrate a case study where an AI-written HDL is tapeout for an 8-bit accumulator-based microprocessor.
• Identify practical recommendations and limitations for integrating conversational LLMs into hardware CAD workflows.

Proposed method

• Conducting an observational study by co-designing an 8-bit accumulator-based processor with ChatGPT-4 under real hardware constraints.
• Partitioning design work into conversation threads to manage the LLM context window and maintain a base specification.
• Iteratively debugging and repairing HDL and ISA definitions with human oversight and targeted prompts.
• Synthesizing the processor using OpenLane for ASIC Tiny Tapeout and simulating on FPGA to compare timing and power estimates.
• Providing and analyzing full conversation logs and artifacts to evaluate reproducibility and practicality.

Experimental results

Research questions

• RQ1 Can a conversational LLM effectively co-design an HDL-based processor under strict hardware constraints?
• RQ2 What are the practical benefits and limitations of interactive AI assistance in HDL writing, verification, and tapeout workflows?
• RQ3 How does the quality of AI-generated HDL and ISA definitions impact synthesis results and post-synthesis timing/power estimates?
• RQ4 What strategies (e.g., thread-based prompts, restarts) improve reliability and correctness when using LLMs for hardware design?

Key findings

• ChatGPT-4 produced relatively high-quality Verilog code and aided rapid design space exploration.
• The process required human intervention to correct specifications and implementation errors and to generate testbenches and verification code.
• The processor was ultimately synthesized and taped out using Tiny Tapeout with OpenLane, yielding a 125 kHz ASIC clock constraint and specific power estimates.
• The case study demonstrates the potential of LLMs as design assistants rather than sole designers in hardware engineering.
• Security analysis via CWEAT found no hardware CWEs in the Verilog produced, while acknowledging limitations in verification tooling with LLMs.