[Paper Review] CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning

Sahibia Kaur Vohra, Sherin Ann Thomas+2 more|arXiv (Cornell University)|Apr 9, 2022

Advanced Memory and Neural Computing4 citations

TL;DR

This paper presents the first full CMOS circuit-level implementation of a spiking neural network (SNN) with on-chip unsupervised STDP learning for pattern recognition, using 180 nm CMOS technology without FPGAs or external processors. It achieves 100% classification accuracy on 5×3 pixel patterns and demonstrates rate-based BCM learning for heart rate classification using the same STDP circuit, validating robustness under process and temperature variations.

ABSTRACT

Computation on a large volume of data at high speed and low power requires energy-efficient computing architectures. Spiking neural network (SNN) with bio-inspired spike-timing-dependent plasticity learning (STDP) is a promising solution for energy-efficient neuromorphic systems than conventional artificial neural network (ANN). Previous works on SNN with STDP learning primarily uses memristive devices which are difficult to fabricate. Some reported works on SNN makes use of memristor macro models, which are software-based and cannot give complete insight into circuit implementation challenges. This article presents for the first time, a full circuit-level implementation of the SNN system featuring on-chip unsupervised STDP learning in standard CMOS technology. It does not involve the use of FPGAs, CPUs or GPUs for training the neural network. We demonstrated the complete circuit-level design, implementation and simulation of SNN with on-chip training and inference for pattern classification using 180 nm CMOS technology. A comprehensive comparison of the proposed SNN circuit with the previous related work is also presented. To demonstrate the versatility of the CMOS synapse circuit for application scenarios requiring rate-based learning, we have tuned the pair-based STDP circuit to obtain Bienenstock-Cooper-Munro (BCM) characteristics and applied it to heart rate classification.

Motivation & Objective

• To develop a fully integrated, hardware-implemented SNN using standard CMOS technology for energy-efficient neuromorphic computing.
• To overcome the limitations of memristor-based SNNs by using CMOS-based memristor emulators for reliable, fabricable, and scalable circuit design.
• To enable on-chip unsupervised STDP learning without relying on FPGAs, CPUs, or GPUs for training.
• To demonstrate the versatility of the STDP circuit for both timing-based (STDP) and rate-based (BCM) learning in a single hardware platform.
• To validate the system’s robustness and accuracy under process, temperature, and noise variations through simulation.

Proposed method

• Design and simulation of a 15-input, 90-synapse, 6-output LIF-based SNN using 180 nm CMOS technology.
• Implementation of a CMOS-based memristor emulator to replace physical memristors and enable full circuit-level integration.
• Integration of a pair-based STDP learning mechanism for on-chip synaptic weight adaptation using spike timing differences.
• Adaptation of the STDP circuit to emulate BCM learning by tuning threshold frequency θ to enable rate-based synaptic plasticity.
• Use of WTA (Winner-Takes-All) mechanism in the output layer for pattern classification.
• Simulation of pattern recognition using spike trains generated from 5×3 pixel images and ECG signals for heart rate classification.

Experimental results

Research questions

• RQ1 Can a fully integrated CMOS-based SNN with on-chip STDP learning be implemented without external training platforms?
• RQ2 How does the CMOS-based memristor emulator perform in replicating the behavior of physical memristors in SNNs?
• RQ3 Can the same STDP circuit be reconfigured to support rate-based BCM learning for alternative applications?
• RQ4 What is the classification accuracy of the SNN under process, temperature, and noise variations?
• RQ5 How effective is the system in classifying heart rate patterns using BCM learning derived from STDP?

Key findings

• The proposed CMOS-based SNN achieved 100% classification accuracy for six 5×3 pixel patterns under ideal and noisy conditions.
• The system demonstrated robust performance under process and temperature variations, confirming circuit stability.
• The same STDP circuit was successfully reconfigured to emulate BCM learning by tuning the threshold frequency θ to 1 Hz and 1.667 Hz for low and high heart rate classification.
• Heart rate classification using ECG data from PhysioBank ATM showed correct classification of 8 out of 10 test cases, with normal, low, and high rates correctly identified based on weight change trends.
• The simulation results matched analytical predictions, validating the accuracy of the CMOS SNN design.
• The system enables in-situ training and inference without external processors, demonstrating a fully hardware-integrated neuromorphic solution.