[Paper Review] Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors

Jyothi Krishna V. S, Shankar Balachandran|arXiv (Cornell University)|Aug 18, 2018

Parallel Computing and Optimization Techniques15 references3 citations

TL;DR

This paper proposes a hardware-aware compiler-enhanced scheduling (CES) framework for OpenMP on big.LITTLE heterogeneous multiprocessors, using compiler transformations and scheduling directives to optimize thread placement based on workload characteristics. The approach reduces runtime by 18% and energy consumption by 14% on average across NPB and FSU benchmarks, outperforming runtime-only scheduling by leveraging static analysis and work-stealing heuristics.

ABSTRACT

Scheduling in Asymmetric Multicore Processors (AMP), a special case of Heterogeneous Multiprocessors, is a widely studied topic. The scheduling techniques which are mostly runtime do not usually consider parallel programming pattern used in parallel programming frameworks like OpenMP. On the other hand, current compilers for these parallel programming platforms are hardware oblivious which prevent any compile-time optimization for platforms like big.LITTLE and has to completely rely on runtime optimization. In this paper, we propose a hardware-aware Compiler Enhanced Scheduling (CES) where the common compiler transformations are coupled with compiler added scheduling commands to take advantage of the hardware asymmetry and improve the runtime efficiency. We implement a compiler for OpenMP and demonstrate its efficiency in Samsung Exynos with big.LITTLE architecture. On an average, we see 18% reduction in runtime and 14% reduction in energy consumption in standard NPB and FSU benchmarks with CES across multiple frequencies and core configurations in big.LITTLE.

Motivation & Objective

• To address the inefficiency of hardware-agnostic compilers in scheduling multithreaded OpenMP programs on heterogeneous multiprocessors like big.LITTLE.
• To improve runtime and energy efficiency by integrating static program analysis with hardware-aware scheduling decisions at compile time.
• To reduce reliance on dynamic runtime scheduling by enabling the compiler to guide thread placement based on workload patterns and core characteristics.
• To evaluate the effectiveness of compiler-directed scheduling across varying core counts, frequencies, and thread workloads on real big.LITTLE hardware.

Proposed method

• The compiler performs static analysis to classify OpenMP work-sharing constructs (e.g., parallel for, sections) based on computational and memory access patterns.
• It applies program transformations such as worklist generation with dynamic load balancing via work-stealing for irregular or load-imbalanced loops.
• The compiler inserts scheduling directives that guide the runtime scheduler to assign specific threads to big or LITTLE cores based on predicted performance and energy impact.
• It supports multiple scheduling policies: static, dynamic, and guided, with transformations tailored to each to minimize overhead and improve load balance.
• The framework adapts to varying hardware configurations (e.g., 2+2, 4+2, 4+4 cores) and frequencies (1.3GHz, 1.9GHz) by re-optimizing thread placement at compile time.
• A prototype compiler was implemented and evaluated on Samsung Exynos with big.LITTLE architecture using NPB and FSU-OpenMP benchmarks.

Experimental results

Research questions

• RQ1 Can a compiler-aware scheduling framework improve runtime and energy efficiency on big.LITTLE architectures compared to pure runtime scheduling?
• RQ2 How does static analysis of OpenMP constructs enable better thread placement decisions than dynamic heuristics alone?
• RQ3 To what extent does work-stealing in transformed loops improve performance and scalability across different core configurations?
• RQ4 How do varying core frequencies and ratios affect the performance and energy gains from compiler-enhanced scheduling?

Key findings

• On average, the CES framework achieved an 18% reduction in execution time and 14% reduction in energy consumption across multiple NPB and FSU benchmarks on big.LITTLE systems.
• For the EP benchmark with work-stealing, the framework achieved a 20% improvement in runtime and 8% in energy efficiency, demonstrating scalability with workload size.
• The energy savings were particularly high (28%) for the IS benchmark at lower LITTLE core frequency (1GHz), indicating better load balancing under asymmetric frequency scaling.
• The framework maintained consistent performance improvements across different core ratios (2+2, 4+2, 4+4), showing adaptability to hardware configuration changes.
• The modified multitask benchmark showed significant energy benefits (up to 28%) when section affinity was enforced, reducing scheduling variability and improving predictability.
• The approach outperformed HMP scheduling by reducing runtime variability and improving energy efficiency through static analysis and targeted compiler transformations.