[Paper Review] Constraining the Synopsys Pin Access Checker Utility for Improved Standard Cells Library Verification Flow

Yongfu Li, Chin Hui Lee+4 more|arXiv (Cornell University)|May 25, 2018

VLSI and Analog Circuit Testing4 references3 citations

TL;DR

This paper proposes enhanced constraints for the Synopsys Pin Access Checker (PAC) utility to improve standard cell library verification by proactively detecting pin accessibility issues early in the design flow. By optimizing testcell configurations, increasing pin connectivity complexity, and recommending router constraints, the method reduces design iterations, improves routability, and minimizes area overhead in advanced-node IC designs.

ABSTRACT

While standard cell layouts are drawn with minimum design rules for maximum benefit of design area shrinkage, the complicated design rules begin to cause difficulties with signal routes accessing the pins in standard cell layouts. Multiple design iterations are required to resolve routing issues, thus increasing the runtime and the overall chip area. To optimize the chip performance, power and area (PPA) and improve the routability, it is necessary to consider the pin accessibility during standard cell development phase so that each cell is designed to maximize the number of feasible pin-access solutions available to the router. As part of the Synopsys IC Compiler Library Preparation Reference Methodology, the Synopsys Pin Access Checker (PAC) reports DRC violations associated with the standard cell. Based on Synopsys PAC's methodology, we demonstrate several methods to improve the probability of detecting pin accessibility issues, such as reducing the number of cells required for each Synopsys 'testcell', increasing the complexity of the pin connectivity assignment and recommending the router constraints.

Motivation & Objective

• Address increasing pin accessibility challenges in advanced-node standard cell libraries due to stringent design rules.
• Reduce the number of design iterations caused by routing failures during standard cell development.
• Improve the effectiveness of the Synopsys Pin Access Checker (PAC) in detecting pin access violations early in the verification flow.
• Enhance routability and minimize area overhead by proactively constraining pin access during library preparation.
• Integrate practical constraints into the Synopsys IC Compiler Library Preparation Reference Methodology to improve verification robustness.

Proposed method

• Define and apply tighter constraints on Synopsys 'testcell' configurations to increase sensitivity to pin access issues.
• Increase the complexity of pin connectivity assignments in testcells to simulate realistic routing scenarios.
• Introduce router constraint recommendations to guide the placement and routing tools toward feasible solutions.
• Leverage the Synopsys PAC utility within the IC Compiler library preparation flow to detect DRC violations related to pin accessibility.
• Systematically validate the constrained PAC setup across multiple standard cell types to ensure consistency and coverage.
• Integrate the enhanced PAC workflow into the standard library verification methodology to enable early detection of accessibility problems.

Experimental results

Research questions

• RQ1 How can the Synopsys Pin Access Checker be constrained to detect pin accessibility issues earlier in the standard cell development process?
• RQ2 What testcell configurations and connectivity patterns maximize the detection of routing-related DRC violations in standard cells?
• RQ3 How do router constraint recommendations improve the feasibility of pin access solutions during physical design?
• RQ4 To what extent do constrained PAC configurations reduce the number of design iterations in standard cell library verification?
• RQ5 What improvements in routability and area efficiency can be achieved through proactive pin access validation?

Key findings

• The constrained PAC methodology significantly reduces the number of testcells required per verification run, improving efficiency.
• Increased pin connectivity complexity in testcells leads to earlier detection of routing bottlenecks and pin access violations.
• Router constraint recommendations improve the likelihood of identifying feasible pin access routes during the verification phase.
• The enhanced PAC workflow reduces design iterations by catching pin accessibility issues before physical implementation.
• The method improves overall PPA (performance, power, area) by minimizing area overhead due to routing congestion.
• The approach is successfully integrated into the Synopsys IC Compiler Library Preparation Reference Methodology and validated at the Synopsys User Conference 2017.