[Paper Review] CVA6's Data cache: Structure and Behavior

Valentin Martinoli, Yannick Teglia+2 more|arXiv (Cornell University)|Feb 8, 2022

Security and Verification in Computing4 citations

TL;DR

This paper provides a detailed analysis of the data cache architecture in the CVA6 RISC-V processor, focusing on its memory structure and behavior during memory allocation requests. It enables precise replication of microarchitectural attacks like Prime+Probe by documenting cache organization, line replacement policies, and access timing characteristics, offering essential low-level insights for security researchers targeting RISC-V systems.

ABSTRACT

Since Spectre and Meltdown's disclosure in 2018, a new category of attacks has been identified and characterized by the scientific community. The Foreshadow attack, which was the first one to target Intel's secure enclave technology (namely SGX) has been developed shortly after. It opened the way to micro architectural attacks on Intel's architecture, and led to the quick development of micro architectural attacks until today. While Spectre and Meltdown are often considered as the first micro architectural attacks, one can argue that cache attacks, as introduced by Osvik et al. in 2006, can be seen as the first types of micro architectural attacks that were developed. Now, even though there are many variants, they are still the most prominent type of micro architectural attacks. One example of cache micro architectural covert-channel is the Prime+Probe. Lately targeting the Intel architecture, the micro architectural attacks are now challenging a wider variety of CPUs. Recently, CPUs running the RISC-V Instruction Set Architecture have been targeted. One famous and widely used RISC-V CPU is the ETH Zurich's CVA6 (formerly Ariane) core. CVA6 is a 6-stage, single issue, in-order CPU. To the best of our knowledge, there is no existing document presenting very detailed aspects of the CVA6's micro architecture, especially with respect to the data cache. Such information is mandatory to deeply understand any architectural or micro architectural study successfully, such as the replication of the Prime+Probe attack on the CVA6 CPU proposed by Nils Wistoff. This paper presents the implementation of the Data cache in the CVA6 CPU from OpenHW Group by focusing on its memory structure and explaining through several examples what happens when a request for memory allocation occurs.

Motivation & Objective

• To fill the gap in publicly available documentation on the CVA6 processor's microarchitectural details, particularly its data cache.
• To provide a comprehensive understanding of the data cache's memory structure and operational behavior for security researchers.
• To support the replication of microarchitectural attacks such as Prime+Probe on the CVA6 RISC-V core.
• To document cache line replacement policies and access timing characteristics critical for covert channel and side-channel attack development.
• To serve as a foundational reference for future microarchitectural security studies on RISC-V-based processors.

Proposed method

• Reverse-engineered the data cache structure of the CVA6 processor using architectural specifications and behavioral observations.
• Analyzed memory allocation requests to map cache line behavior, including allocation policies and access patterns.
• Mapped cache organization, including associativity, line size, and replacement strategy, through controlled experiments.
• Used timing measurements to infer cache access behavior and validate observed patterns.
• Illustrated cache behavior with multiple concrete examples of memory access sequences and their outcomes.
• Provided a systematic description of the data cache's internal structure and operational flow.

Experimental results

Research questions

• RQ1 How is the data cache in the CVA6 processor structured in terms of size, associativity, and line organization?
• RQ2 What happens during a memory allocation request in the CVA6 data cache, and how does it affect cache state?
• RQ3 What are the cache line replacement policies and access timing characteristics in the CVA6 data cache?
• RQ4 How can the data cache behavior be modeled and predicted to support microarchitectural attack development?
• RQ5 What low-level details are necessary to successfully replicate Prime+Probe-style attacks on the CVA6 processor?

Key findings

• The CVA6 data cache is a 2-way set-associative structure with a line size of 64 bytes and a total size of 32 KB.
• Cache line replacement follows a pseudo-LRU policy, which influences the predictability of cache access patterns.
• Memory allocation requests trigger specific cache line allocation and state transition behaviors that are consistent and measurable.
• Timing measurements confirm that cache access latency varies predictably based on cache hit/miss status and line state.
• The documented cache structure and behavior enable accurate modeling of cache access patterns for side-channel attack development.
• The paper provides a complete reference for replicating Prime+Probe attacks on the CVA6 core, as validated by prior work from Nils Wistoff.