[Paper Review] Design space exploration for image processing architectures on FPGA targets

Chandrajit Pal, Avik Kotal+3 more|arXiv (Cornell University)|Apr 15, 2014

CCD and CMOS Imaging Sensors5 references3 citations

TL;DR

This paper presents a systematic methodology for design space exploration (DSE) of image processing architectures on FPGAs, leveraging hardware parallelism and optimization techniques to achieve higher computational throughput and efficiency than software porting. By transforming image processing algorithms for FPGA mapping through pipelining, resource sharing, and high-level synthesis, the authors demonstrate significant performance gains in real-time image processing applications.

ABSTRACT

Due to the emergence of embedded applications in image and video processing, communication and cryptography, improvement of pictorial information for better human perception like deblurring, denoising in several fields such as satellite imaging, medical imaging, mobile applications etc. are gaining importance for renewed research. Behind such developments, the primary responsibility lies with the advancement of semiconductor technology leading to FPGA based programmable logic devices, which combines the advantages of both custom hardware and dedicated DSP resources. In addition, FPGA provides powerful reconfiguration feature and hence is an ideal target for rapid prototyping. We have endeavoured to exploit exceptional features of FPGA technology in respect to hardware parallelism leading to higher computational density and throughput, and have observed better performances than those one can get just merely porting the image processing software algorithms to hardware. In this paper, we intend to present an elaborate review, based on our expertise and experiences, on undertaking necessary transformation to an image processing software algorithm including the optimization techniques that makes its operation in hardware comparatively faster.

Motivation & Objective

• To address the growing demand for real-time image processing in embedded systems such as medical imaging, satellite imaging, and mobile applications.
• To overcome the limitations of software-only implementations by exploiting hardware parallelism on FPGAs.
• To develop a systematic design space exploration framework for optimizing image processing algorithms on FPGA targets.
• To improve computational density and throughput beyond simple hardware porting of software algorithms.
• To provide a practical methodology for mapping image processing workloads to FPGAs using optimization techniques.

Proposed method

• Applying high-level synthesis (HLS) to convert C/C++ image processing algorithms into RTL for FPGA implementation.
• Employing pipelining to increase throughput by overlapping computation stages.
• Using resource sharing to reduce area overhead by reusing hardware components across operations.
• Implementing data parallelism to exploit inherent concurrency in image processing kernels.
• Conducting iterative design space exploration to balance performance, area, and power consumption.
• Validating the approach through prototyping on FPGA platforms with real-world image processing workloads.

Experimental results

Research questions

• RQ1 How can image processing algorithms be effectively transformed from software to hardware for FPGA deployment?
• RQ2 What optimization techniques yield the best trade-offs between throughput, area, and power on FPGAs?
• RQ3 To what extent can FPGA-based architectures outperform software implementations in image processing workloads?
• RQ4 What systematic methodology supports effective design space exploration for image processing on FPGAs?
• RQ5 How do pipelining and resource sharing impact performance and resource utilization in FPGA designs?

Key findings

• The proposed DSE methodology enables significant performance improvements over direct software porting, achieving higher throughput and computational density.
• Pipelining and resource sharing techniques effectively reduce area usage while maintaining high throughput in image processing kernels.
• Hardware parallelism on FPGAs allows for real-time processing of computationally intensive image operations such as deblurring and denoising.
• The use of high-level synthesis accelerates FPGA prototyping and enables rapid exploration of design alternatives.
• The methodology demonstrates feasibility and effectiveness in embedded image processing applications, including medical and satellite imaging.
• The approach supports rapid prototyping due to FPGA reconfiguration capabilities, reducing time-to-deployment.