[Paper Review] Development of a pipeline CAMAC controller with PC/104-Plus single board computer

Y. Yasu, Eiji Inoue+8 more|ArXiv.org|Jul 15, 2003

Parallel Computing and Optimization Techniques7 citations

TL;DR

This paper presents a high-speed pipeline CAMAC controller built using a PC/104-Plus single board computer, featuring fully pipelined command and data paths that achieve a peak data rate of approximately 3 MB/sec with 24-bit data precision. The design enables efficient data acquisition and coexistence with other systems like VME through event numbering, offering a novel architecture that significantly improves performance over traditional CAMAC controllers.

ABSTRACT

A pipeline CAMAC controller with PC/104-Plus single board computer has been developed. The architecture of the pipeline CAMAC controller is completely different from that of traditional CAMAC controller. The pipeline CAMAC controller adopted truly pipelined command and data paths from/to computer memory to/from CAMAC. The pipeline method enabled the controller maximum speed of CAMAC, approximately up to 3 MB/sec with 24-bit data. The controller also has a DAQ function such as event numbering for co-existence with other equipment such as VME. Not only the functionality and the performance but also the pipeline architecture and the design concept are described.

Motivation & Objective

• To develop a high-performance CAMAC controller for use in high-energy and nuclear physics experiments.
• To overcome the performance limitations of traditional CAMAC controllers by implementing a pipelined architecture.
• To enable efficient data acquisition and synchronization with other systems such as VME through event numbering functionality.
• To integrate a compact, embedded solution using PC/104-Plus SBC for real-time data processing.
• To demonstrate a novel controller architecture that maximizes CAMAC data transfer speed through pipelining of commands and data.

Proposed method

• The controller uses a pipelined architecture to enable concurrent processing of commands and data between the PC/104-Plus SBC and CAMAC modules.
• Data and command paths are independently pipelined from computer memory to and from the CAMAC system, reducing latency and increasing throughput.
• The system implements event numbering to support coexistence with other data acquisition systems like VME, ensuring synchronization across heterogeneous equipment.
• The controller is built around a PC/104-Plus single board computer, providing a compact, embedded platform for real-time data handling.
• The design emphasizes hardware-software co-design to maximize data transfer efficiency and minimize bottlenecks.
• The architecture supports 24-bit data precision, enabling high-resolution data acquisition in experimental physics.

Experimental results

Research questions

• RQ1 How can pipelined data and command paths be implemented in a CAMAC controller to maximize data throughput?
• RQ2 What performance improvements can be achieved over traditional CAMAC controllers using a pipelined architecture?
• RQ3 How can event numbering be integrated into a CAMAC controller to enable synchronization with VME systems?
• RQ4 What are the practical limitations and design trade-offs in implementing a high-speed CAMAC controller on a PC/104-Plus SBC?
• RQ5 To what extent can a compact, embedded system achieve high-speed data acquisition comparable to dedicated CAMAC controllers?

Key findings

• The pipeline CAMAC controller achieves a maximum data transfer rate of approximately 3 MB/sec with 24-bit data precision, significantly exceeding typical performance of conventional CAMAC controllers.
• The pipelined command and data paths allow concurrent operations, reducing idle time and maximizing utilization of the CAMAC interface.
• The integration of event numbering enables seamless coexistence with other data acquisition systems such as VME, supporting synchronized data collection.
• The use of a PC/104-Plus single board computer provides a compact, reliable, and cost-effective platform for embedded data acquisition.
• The controller's architecture is fundamentally different from traditional designs, emphasizing throughput and real-time performance through hardware pipelining.
• The system was successfully demonstrated at the CHEP2003 conference as a poster, validating its functionality and performance in a real-world experimental context.