[Paper Review] Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators

Weiwen Jiang, Qiuwen Lou+5 more|arXiv (Cornell University)|Oct 31, 2019

Advanced Memory and Neural Computing47 references4 citations

TL;DR

This paper proposes NACIM, a cross-layer co-exploration framework for computing-in-memory (CiM) neural accelerators that jointly optimizes device type, circuit topology, and neural architecture while accounting for device variation. By integrating variation-aware training and multi-objective optimization, NACIM achieves 0.45% accuracy loss under variation—significantly better than the 76.44% loss in state-of-the-art NAS—while reaching 16.3 TOPs/W energy efficiency, a 3.17× improvement over prior work.

ABSTRACT

Co-exploration of neural architectures and hardware design is promising to simultaneously optimize network accuracy and hardware efficiency. However, state-of-the-art neural architecture search algorithms for the co-exploration are dedicated for the conventional von-neumann computing architecture, whose performance is heavily limited by the well-known memory wall. In this paper, we are the first to bring the computing-in-memory architecture, which can easily transcend the memory wall, to interplay with the neural architecture search, aiming to find the most efficient neural architectures with high network accuracy and maximized hardware efficiency. Such a novel combination makes opportunities to boost performance, but also brings a bunch of challenges. The design space spans across multiple layers from device type, circuit topology to neural architecture. In addition, the performance may degrade in the presence of device variation. To address these challenges, we propose a cross-layer exploration framework, namely NACIM, which jointly explores device, circuit and architecture design space and takes device variation into consideration to find the most robust neural architectures. Experimental results demonstrate that NACIM can find the robust neural network with 0.45% accuracy loss in the presence of device variation, compared with a 76.44% loss from the state-of-the-art NAS without consideration of variation; in addition, NACIM achieves an energy efficiency up to 16.3 TOPs/W, 3.17X higher than the state-of-the-art NAS.

Motivation & Objective

• To address the performance bottleneck of von-Neumann architectures by leveraging computing-in-memory (CiM) to transcend the memory wall.
• To enable joint optimization across device, circuit, and neural architecture design layers for maximal hardware efficiency and network accuracy.
• To mitigate the impact of device variation in emerging non-volatile memory devices on neural network inference accuracy.
• To develop a scalable, multi-objective co-exploration framework that simultaneously optimizes accuracy, energy, latency, area, and hardware lifetime.
• To demonstrate that architecture search with variation-aware training yields significantly more robust and efficient neural accelerators than fixed-architecture approaches.

Proposed method

• NACIM employs a multi-objective reinforcement learning framework that jointly explores device type, circuit topology, and neural architecture design spaces.
• It integrates a variation-aware training procedure that simulates device non-idealities during backpropagation to improve robustness.
• The framework uses a reward function combining normalized hardware efficiency (weighted by latency, area, and energy) and inference accuracy.
• Monte Carlo sampling is used to estimate the impact of device variation during training, ensuring robustness across device parameter distributions.
• The search space includes diverse neural architectures such as VGG-11, ResNet-like structures, and U-Net-style encoders, enabling exploration of efficient, task-specific designs.
• Hardware metrics such as EDP and area are normalized and used as part of the hardware efficiency objective to enable Pareto-optimal trade-offs.

Experimental results

Research questions

• RQ1 Can co-exploration of device, circuit, and neural architecture design spaces in CiM accelerators lead to better accuracy and hardware efficiency than conventional NAS?
• RQ2 How does device variation affect the inference accuracy of neural networks mapped to CiM hardware, and can this be mitigated during training?
• RQ3 What is the impact of architecture search on the robustness and efficiency of CiM-based neural accelerators under non-ideal device behavior?
• RQ4 Can a unified framework simultaneously optimize for accuracy, energy, latency, area, and hardware lifetime in CiM accelerators?
• RQ5 How does the proposed NACIM framework scale across different backbone architectures and machine learning tasks?

Key findings

• NACIM achieves 16.3 TOPs/W energy efficiency, representing a 3.17× improvement over state-of-the-art NAS methods.
• Under device variation, NACIM incurs only 0.45% accuracy loss, compared to a 76.44% loss in variation-unaware NAS, demonstrating superior robustness.
• For CIFAR-10 with a ResNet-like backbone, NACIM improves accuracy from 72.18% (baseline) to 73.45% while reducing area by 23.3% and EDP by 52.4%.
• On the VLS object segmentation task, NACIM achieves 93.12% accuracy with 4.75×10⁸ μm² area and 5.54×10¹⁵ pJ·ns EDP, outperforming the baseline in both accuracy and efficiency.
• The framework successfully identifies smaller, more efficient architectures (e.g., RLS) that achieve higher accuracy and lower EDP than larger backbones like VGG-11.
• Variation-aware training significantly improves inference robustness, with accuracy gains of 9.8%, 9.6%, and 0.525 IOU improvements on RLS, VLS, and EDS tasks, respectively, compared to variation-unaware training.