[Paper Review] Do Your Cores Play Nicely? A Portable Framework for Multi-core Interference Tuning and Analysis

Dan Iorga, Tyler Sorensen+1 more|arXiv (Cornell University)|Sep 13, 2018

Parallel Computing and Optimization Techniques16 references3 citations

TL;DR

This paper proposes a portable, black-box auto-tuning framework that automatically identifies effective parameter configurations for 'enemy processes'—synthetic workloads designed to induce multi-core interference—on various architectures. By using random search, simulated annealing, or Bayesian optimization to tune these processes, the method achieves slowdowns in 98% of benchmark/chip combinations, matching or exceeding manually crafted enemy processes in effectiveness while eliminating the need for microarchitectural expertise per platform.

ABSTRACT

Multi-core architectures can be leveraged to allow independent processes to run in parallel. However, due to resources shared across cores, such as caches, distinct processes may interfere with one another, e.g. affecting execution time. Analysing the extent of this interference is difficult due to: (1) the diversity of modern architectures, which may contain different implementations of shared resources, and (2) the complex nature of modern processors, in which interference might arise due to subtle interactions. To address this, we propose a black-box auto-tuning approach that searches for processes that are effective at causing slowdowns for a program when executed in parallel. Such slowdowns provide lower bounds on worst-case execution time; an important metric in systems with real-time constraints. Our approach considers a set of parameterised "enemy" processes and "victim" programs, each targeting a shared resource. The autotuner searches for enemy process parameters that are effective at causing slowdowns in the victim programs. The idea is that victim programs behave as a proxy for shared resource usage of arbitrary programs. We evaluate our approach on: 5 different chips; 3 resources (cache, memory bus, and main memory); and consider several search strategies and slowdown metrics. Using enemy processes tuned per chip, we evaluate the slowdowns on the autobench and coremark benchmark suites and show that our method is able to achieve slowdowns in 98% of benchmark/chip combinations and provide similar results to manually written enemy processes.

Motivation & Objective

• To address the portability and effectiveness limitations of manually designed enemy processes for measuring multi-core interference.
• To enable automatic discovery of interference-inducing process parameters without requiring low-level microarchitectural knowledge of target platforms.
• To develop a unified, reusable framework that can be applied across diverse multi-core architectures (ARM and x86) to quantify worst-case execution time (WCET) degradation.
• To evaluate whether auto-tuned enemy processes can match or exceed the performance of hand-crafted ones in inducing measurable slowdowns on real benchmarks.
• To demonstrate that the method reliably identifies high-impact interference scenarios across multiple shared resources (cache, memory bus, main memory).

Proposed method

• The framework uses parameterized 'enemy templates' targeting specific shared resources—such as cache lines accessed with stride patterns or memory bandwidth with repeated accesses.
• It applies black-box optimization strategies (random search, simulated annealing, Bayesian optimization) to tune enemy process parameters (e.g., buffer size, stride, access pattern) for maximum slowdown on a 'victim' program.
• Victim programs are selected to be sensitive to specific interference paths (e.g., vector addition for cache interference), serving as proxies for real application behavior.
• The method performs a two-level tuning: first optimizing enemy parameters per interference path, then combining tuned enemies into a hostile environment for evaluation.
• Search strategies are evaluated based on their ability to find high-slowdown configurations efficiently, with performance measured using statistical significance and magnitude of slowdown.
• The framework is evaluated on five different chips (including ARM and x86), using standard benchmarks (autobench, coremark), and compared against hand-tuned enemy processes from prior work.

Experimental results

Research questions

• RQ1 Can an auto-tuning approach effectively discover parameter configurations for enemy processes that induce significant slowdowns on victim programs across diverse multi-core architectures?
• RQ2 How does the performance of auto-tuned enemy processes compare to manually crafted ones in terms of induced slowdown and statistical significance?
• RQ3 Which optimization strategy (random search, simulated annealing, Bayesian optimization) yields the most effective and efficient discovery of high-impact interference configurations?
• RQ4 To what extent can the framework be ported across different chips without re-implementation, given varying microarchitectural details?
• RQ5 Does the auto-tuned hostile environment reliably produce measurable and meaningful worst-case execution time bounds across multiple shared resources (cache, memory bus, main memory)?

Key findings

• The auto-tuning framework successfully induced measurable slowdowns in 98% of all benchmark and chip combinations evaluated, demonstrating high reliability across diverse architectures.
• In 52% of cases, the auto-tuned hostile environments achieved statistically significant higher slowdowns than hand-tuned counterparts, with overlapping confidence intervals in the remaining 48%.
• The method achieved comparable or better performance than manually written enemy processes, even without access to low-level microarchitectural details of the target platforms.
• Bayesian optimization and simulated annealing outperformed random search in terms of convergence speed and effectiveness in finding high-slowdown configurations.
• The framework demonstrated strong portability: the same enemy templates and victim programs could be reused across different chips after auto-tuning per platform, eliminating the need for architecture-specific hand-coding.
• The approach successfully detected hidden interference patterns not easily predictable from documentation, highlighting its ability to uncover subtle microarchitectural interactions.