[Paper Review] Efficient Sealable Protection Keys for RISC-V

Leila Delshadtehrani, Sadullah Canakci+2 more|arXiv (Cornell University)|Dec 4, 2020

Security and Verification in Computing16 references4 citations

TL;DR

This paper proposes SealPK, an efficient intra-process memory isolation mechanism for RISC-V that supports up to 1024 protection domains by utilizing 10 unused bits in Sv-39 page table entries. It prevents the pkey use-after-free vulnerability via OS-level lazy de-allocation and introduces three novel sealing features to protect domain permissions, pages, and keys from tampering, demonstrated via FPGA prototype with minimal performance overhead and successful shadow stack isolation.

ABSTRACT

With the continuous increase in the number of software-based attacks, there has been a growing effort towards isolating sensitive data and trusted software components from untrusted third-party components. A hardware-assisted intra-process isolation mechanism enables software developers to partition a process into isolated components and in turn secure sensitive data from untrusted components. However, most of the existing hardware-assisted intra-process isolation mechanisms in modern processors, such as ARM and IBM Power, rely on costly kernel operations for switching between trusted and untrusted domains. Recently, Intel introduced a new hardware feature for intra-process memory isolation, called Memory Protection Keys (MPK), which enables a user-space process to switch the domains in an efficient way. While the efficiency of Intel MPK enables developers to leverage it for common use cases such as Code-Pointer Integrity, the limited number of unique domains (16) prohibits its use in cases such as OpenSSL where a large number of domains are required. Moreover, Intel MPK suffers from the protection key use-after-free vulnerability. To address these shortcomings, in this paper, we propose an efficient intra-process isolation technique for the RISC-V open ISA, called SealPK, which supports up to 1024 unique domains. SealPK prevents the protection key use-after-free problem by leveraging a lazy de-allocation approach. To further strengthen SealPK, we devise three novel sealing features to protect the allocated domains, their associated pages, and their permissions from modifications or tampering by an attacker. To demonstrate the feasibility of our design, we implement SealPK on a RISC-V Rocket processor, provide the OS support for it, and prototype our design on an FPGA. We demonstrate the efficiency of SealPK by leveraging it to implement an isolated shadow stack on our FPGA prototype.

Motivation & Objective

• Address the limited scalability of Intel MPK, which supports only 16 protection keys, by enabling up to 1024 domains in RISC-V.
• Mitigate the pkey use-after-free vulnerability inherent in Intel MPK by introducing an OS-level lazy de-allocation mechanism that tracks domain reference counts.
• Prevent unauthorized modification of protection domains, their pages, and permission bits by an attacker through three novel sealing features.
• Demonstrate the feasibility and efficiency of SealPK by implementing it on a RISC-V Rocket core FPGA prototype with full OS support.
• Enable secure, high-performance intra-process isolation for real-world workloads such as OpenSSL and shadow stack protection.

Proposed method

• Leverage 10 unused bits in Sv-39 page table entries (PTEs) to encode protection keys, enabling 2^10 = 1024 unique domains.
• Implement a lazy de-allocation mechanism at the OS level that defers the invalidation of a protection key until all associated pages are freed.
• Introduce a dedicated 2KB private key register (PKR) to store protection key permissions, accessed in the same cycle as page table lookups.
• Design three sealing features: (1) domain sealing to protect domain integrity, (2) page sealing to prevent unauthorized page modifications, and (3) permission sealing to restrict WRPKRU instructions to a single trusted memory range per key.
• Use a custom RoCC instruction to interface with PKR and enforce sealing policies at runtime.
• Integrate SealPK into the RISC-V Rocket core, extend the OS with domain management and reference counting, and prototype the system on an FPGA.

Experimental results

Research questions

• RQ1 Can a scalable, secure intra-process memory isolation mechanism be built on the open RISC-V ISA that supports more than 16 domains?
• RQ2 How can the pkey use-after-free vulnerability be eliminated without relying on kernel-level enforcement or complex binary instrumentation?
• RQ3 To what extent can hardware-enforced sealing of domains, pages, and permissions prevent tampering by malicious components?
• RQ4 What is the performance and area overhead of integrating such a mechanism into a RISC-V processor core?
• RQ5 Can SealPK be effectively used to secure critical security primitives like a shadow stack in practice?

Key findings

• SealPK supports up to 1024 unique protection domains by utilizing 10 unused bits in Sv-39 PTEs, significantly exceeding Intel MPK’s 16-domain limit.
• The OS-level lazy de-allocation mechanism effectively prevents the pkey use-after-free vulnerability by deferring key invalidation until all pages are freed.
• The FPGA prototype shows only 5.62% LUT and 2.72% FF area overhead, with estimated power overhead under 5%, indicating low hardware cost.
• SealPK introduces three novel sealing features that protect domain integrity, page contents, and permission bits from runtime manipulation.
• The prototype achieved an average performance overhead of 21.00%, 14.81%, and 8.52% for SPEC2000, SPEC2006, and MiBench workloads, respectively, demonstrating practical efficiency.
• SealPK successfully enabled the implementation of an isolated shadow stack on the FPGA prototype, validating its real-world applicability in securing control-flow integrity.