[Paper Review] Evaluating Row Buffer Locality in Future Non-Volatile Main Memories

Justin Meza, Li Jing+1 more|arXiv (Cornell University)|Jun 29, 2018

Parallel Computing and Optimization Techniques23 references23 citations

TL;DR

This paper proposes a novel NVM memory architecture that reorganizes the data path to enable small row buffers without area penalty, leveraging non-destructive reads in PCM and STT-RAM. It achieves up to 67% lower dynamic energy than DRAM in multi-core systems, with minimal performance loss and viable endurance even under high contention.

ABSTRACT

DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low. Unfortunately, system-level trends such as increased memory contention in multi-core architectures and data mapping schemes that improve memory parallelism may cause only a small amount of the buffered data to be accessed. This makes buffering large amounts of data on every memory array access energy-inefficient. Emerging non-volatile memories (NVMs) such as PCM, STT-RAM, and RRAM, however, do not have destructive read operations, opening up opportunities for employing small row buffers without incurring additional area penalty and/or design complexity. In this work, we discuss architectural changes to enable small row buffers at a low cost in NVMs. We provide a memory access protocol, energy model, and timing model to enable further system-level evaluation. We evaluate the system-level tradeoffs of employing different row buffer sizes in NVM main memories in terms of energy, performance, and endurance, with different data mapping schemes. We find that on a multi-core CMP system, reducing the row buffer size can greatly reduce main memory dynamic energy compared to a DRAM baseline with large row sizes, without greatly affecting endurance, and for some memories, leads to improved performance.

Motivation & Objective

• To address the energy inefficiency of large row buffers in DRAM-based main memories under multi-core workloads.
• To explore architectural changes enabling small row buffers in non-volatile memories (NVMs) like PCM and STT-RAM.
• To design a new memory access protocol and energy/timing models for system-level evaluation of NVM main memories.
• To evaluate the trade-offs of row buffer size on energy, performance, and endurance in multi-core CMP systems.
• To demonstrate that small row buffers in NVMs can significantly reduce dynamic energy without sacrificing durability or performance.

Proposed method

• Reorganizes the NVM data path by swapping the column multiplexer and row buffer to enable selective sensing of small data portions.
• Proposes a unified read/write data path compatible with standard JEDEC DDRx interfaces, avoiding interface complexity.
• Develops a custom memory access protocol that supports small row buffers and relaxes timing constraints due to non-destructive reads.
• Creates technology-specific energy and timing models for PCM and STT-RAM based on underlying device parameters.
• Evaluates the architecture using cycle-accurate simulation across multi-core CMP workloads with varying data mapping schemes.
• Uses wear-leveling and e-DRAM caching to model long-term endurance and reduce write amplification.

Experimental results

Research questions

• RQ1 How does reducing row buffer size affect dynamic energy consumption in NVM main memories compared to DRAM?
• RQ2 Can small row buffers in NVMs maintain or improve performance under multi-core memory contention?
• RQ3 What is the impact of row buffer size on NVM endurance, especially under high write workloads?
• RQ4 How do different data mapping schemes (e.g., row vs. block interleaving) interact with small row buffers in NVM systems?
• RQ5 To what extent can the new access protocol and architecture reduce energy waste without increasing area or complexity?

Key findings

• NVM main memories with small row buffers reduce dynamic energy by up to 67% compared to DRAM with large row buffers.
• Performance degradation is minimal; STT-RAM with small row buffers even outperforms DRAM due to relaxed timing constraints.
• Endurance remains viable: all configurations support at least five years of continuous operation, with over ten years when paired with a 32MB e-DRAM cache.
• Write amplification is slightly reduced with smaller row buffers due to longer request queuing and better write coalescing.
• The addition of a 32MB e-DRAM cache reduces main memory writes by 39% to 47%, significantly improving endurance.
• The proposed architecture enables energy efficiency gains without requiring interface changes or significant area overhead.