[Paper Review] Fakernet -- small and fast FPGA-based TCP and UDP communication

H. Johansson, Anders Furufors+1 more|arXiv (Cornell University)|Mar 27, 2020

Network Traffic and Congestion Control16 references4 citations

TL;DR

Fakernet presents a lightweight, FPGA-based TCP and UDP implementation for high-speed data acquisition systems, using a 16-bit word data-flow architecture to achieve 11.7 MB/s over TCP on a 100 Mbps link with minimal FPGA resources. It enables direct Ethernet connectivity from front-end boards, replacing custom buses and PCIe adapters by leveraging standard network stacks and avoiding special drivers.

ABSTRACT

A common theme of data acquisition systems is the transport of data from digitising front-end modules to stable storage and online analysis. A good choice today is to base this on the ubiquitous, commercially and cheaply available Ethernet technology. A firmware building block to turn already the FPGA of front-end electronics into a TCP data source and UDP control interface using a data-flow architecture is presented. The overall performance targets are to be able to saturate a 1 Gbps network link with outbound data, while using few FPGA resources. The goal is to replace the use of custom data buses and protocols with ordinary Ethernet equipment. These objectives are achieved by being just-enough conforming, such that no special drivers are needed in the PC equipment interfacing with the here presented Fakernet system. An important design choice is to handle all packet-data internally as 16-bit words, thus reducing the clock-speed requirements. An advantageous circumstance is that even at 1 Gbps speeds, for local network segments, the round-trip times are usually well below 500 microseconds. Thus, less than 50 kiB of unacknowledged data needs to be in-flight, allowing to saturate a network link without TCP window scaling. The Fakernet system has so far been shown to saturate a 100 Mbps link at 11.7 MB/s of TCP output data, and able to do 32-bit control register accesses at over 450 kword/s.

Motivation & Objective

• To reduce system cost in data acquisition by replacing custom front-end buses and PCIe adapter cards with standard Ethernet.
• To enable FPGA-based front-end boards to act as native TCP/UDP endpoints using only minimal, efficient firmware.
• To achieve high throughput (saturating 1 Gbps links) while consuming few FPGA resources and avoiding complex protocol features.
• To ensure compatibility with commodity PC network stacks by being 'just-enough' conforming to TCP and UDP standards.
• To eliminate the need for custom OS drivers and DMA programming by using standard Ethernet hardware and protocols.

Proposed method

• The system uses a 16-bit word data-flow architecture to reduce clock speed requirements and FPGA resource usage.
• It implements a minimal, compliant TCP and UDP stack in VHDL, focusing only on essential functionality for local network operation.
• Retransmissions are triggered based on RTT timeout and duplicate ACKs, with a conservative backoff strategy to avoid congestion.
• Round-trip time (RTT) is measured using a counter-based filter that discards measurements during retransmissions.
• The design avoids selective ACKs and window scaling, relying on the assumption of over-provisioned bandwidth in local networks.
• The system uses standard Ethernet PHYs and connectors (e.g., RJ45), enabling integration with commodity network equipment.

Experimental results

Research questions

• RQ1 Can a minimal, FPGA-based TCP/UDP stack achieve high throughput (e.g., saturating 100 Mbps) while consuming few FPGA resources?
• RQ2 How can a lightweight TCP implementation handle packet loss and retransmissions efficiently without full congestion control?
• RQ3 To what extent can standard PC network stacks interoperate with a minimal, 'just-enough' conforming TCP/UDP implementation?
• RQ4 What is the performance impact of avoiding window scaling and selective ACKs in a high-speed data acquisition context?
• RQ5 Can the use of 16-bit word processing reduce clock frequency and FPGA resource usage without compromising throughput?

Key findings

• Fakernet achieved a sustained TCP throughput of 11.7 MB/s on a 100 Mbps network link using only minimal FPGA resources.
• The system supports 32-bit control register accesses at over 450 kword/s, demonstrating low-latency control communication.
• The implementation avoids window scaling and selective ACKs, relying on RTT-based retransmission and duplicate ACK detection for loss recovery.
• Round-trip time (RTT) was measured to be around 100 μs in local network segments, enabling high in-flight data limits without window scaling.
• The retransmission strategy ensures bandwidth consumption drops to a trickle (around 110 Hz) if the receiver loses track, preventing connection starvation.
• The system successfully replaces custom buses and PCIe adapters, enabling direct Ethernet connectivity from FPGA-based front-end boards with no special drivers.