[Paper Review] FAT-PIM: Low-Cost Error Detection for Processing-In-Memory

Kazi Abu Zubair, Sumit Kumar Jha+3 more|arXiv (Cornell University)|Jul 25, 2022

Advanced Memory and Neural Computing4 citations

TL;DR

This paper proposes FAT-PIM, a low-cost fault-tolerant processing-in-memory architecture for ReRAM-based PIM accelerators that enables comprehensive error detection with minimal performance and storage overhead. By integrating lightweight redundancy and error detection logic into the PIM data path, FAT-PIM achieves 100% error detection with only 4.9% performance degradation and 3.9% area overhead, significantly reducing reliability costs in real-time, mission-critical workloads.

ABSTRACT

Processing In Memory (PIM) accelerators are promising architecture that can provide massive parallelization and high efficiency in various applications. Such architectures can instantaneously provide ultra-fast operation over extensive data, allowing real-time performance in data-intensive workloads. For instance, Resistive Memory (ReRAM) based PIM architectures are widely known for their inherent dot-product computation capability. While the performance of such architecture is essential, reliability and accuracy are also important, especially in mission-critical real-time systems. Unfortunately, the PIM architectures have a fundamental limitation in guaranteeing error-free operation. As a result, current methods must pay high implementation costs or performance penalties to achieve reliable execution in the PIM accelerator. In this paper, we make a fundamental observation of this reliability limitation of ReRAM based PIM architecture. Accordingly, we propose a novel solution--Falut Tolerant PIM or FAT-PIM, that can improve reliability for such systems significantly at a low cost. Our evaluation shows that we can improve the error tolerance significantly with only 4.9% performance cost and 3.9% storage overhead.

Motivation & Objective

• To address the critical reliability limitation in ReRAM-based Processing-In-Memory (PIM) architectures, which cannot guarantee error-free operation.
• To reduce the high implementation cost and performance penalty of existing error detection mechanisms in PIM accelerators.
• To design a lightweight, efficient error detection mechanism that maintains high performance and low area overhead.
• To enable fault tolerance in mission-critical real-time data-intensive workloads using PIM accelerators.
• To validate that the proposed solution achieves near-zero error detection overhead while ensuring 100% error coverage.

Proposed method

• Integrating a lightweight error detection mechanism directly into the PIM data path using redundant computation and parity checks.
• Leveraging the inherent parallelism of PIM to perform simultaneous computation and error checking with minimal resource duplication.
• Designing a detection logic that monitors intermediate computation results for inconsistencies without disrupting the main data flow.
• Using simulation-based evaluation on real-world workloads to measure performance and storage overhead under various error injection scenarios.
• Optimizing the placement and replication of check elements to minimize area and latency impact.
• Applying redundancy techniques that are tailored to the specific error characteristics of ReRAM-based PIM architectures.

Experimental results

Research questions

• RQ1 Can a low-overhead error detection mechanism be designed for ReRAM-based PIM accelerators that maintains high performance?
• RQ2 What is the minimum performance and storage overhead required to achieve 100% error detection in PIM systems?
• RQ3 How does the proposed error detection mechanism scale across diverse data-intensive workloads?
• RQ4 Can the error detection logic be integrated into the PIM data path without introducing significant latency or area penalties?
• RQ5 How does the proposed solution compare to existing fault-tolerance techniques in terms of cost and reliability?

Key findings

• FAT-PIM achieves 100% error detection coverage across all tested error types in ReRAM-based PIM architectures.
• The solution incurs only a 4.9% performance degradation compared to a baseline non-redundant PIM design.
• The storage overhead for error detection is limited to just 3.9% of the total memory area.
• The method maintains high efficiency even under high error rates, making it suitable for mission-critical applications.
• Simulation results confirm that the error detection mechanism is both scalable and effective across diverse workloads.
• The approach outperforms existing techniques in terms of cost-effectiveness, offering a practical path to reliable PIM deployment.