[Paper Review] Floating-Point Arithmetic on Round-to-Nearest Representations

Peter Kornerup, Jean‐Michel Muller+1 more|arXiv (Cornell University)|Jan 18, 2012

Numerical Methods and Algorithms6 references4 citations

TL;DR

This paper proposes a novel floating-point representation using RN-coding—based on 2's complement with an appended round-bit—that enables constant-time round-to-nearest rounding via simple truncation. By encoding significands in a canonical signed-digit format, the method eliminates log-time rounding incrementation, enabling faster, simpler arithmetic units with equivalent precision to IEEE-754, while supporting efficient directed roundings via a sticky-bit without incrementation.

ABSTRACT

Recently we introduced a class of number representations denoted RN-representations, allowing an un-biased rounding-to-nearest to take place by a simple truncation. In this paper we briefly review the binary fixed-point representation in an encoding which is essentially an ordinary 2's complement representation with an appended round-bit. Not only is this rounding a constant time operation, so is also sign inversion, both of which are at best log-time operations on ordinary 2's complement representations. Addition, multiplication and division is defined in such a way that rounding information can be carried along in a meaningful way, at minimal cost. Based on the fixed-point encoding we here define a floating point representation, and describe to some detail a possible implementation of a floating point arithmetic unit employing this representation, including also the directed roundings.

Motivation & Objective

• To design a floating-point arithmetic system that enables un-biased round-to-nearest operations in constant time, avoiding the log-time cost of traditional IEEE-754 rounding.
• To simplify hardware implementation of basic arithmetic operations (addition, multiplication, division) by leveraging a canonical encoding of 2's complement with a round-bit.
• To support both round-to-nearest and directed rounding modes (RU, RD, RZ, RA) efficiently, without requiring rounding incrementation.
• To demonstrate that RN-representations preserve precision and accuracy equivalent to IEEE-754 while reducing area and delay in specialized hardware (e.g., ASIC/FPGA).

Proposed method

• Uses a canonical encoding of 2's complement numbers with an appended round-bit, enabling truncation to yield round-to-nearest results in constant time.
• Represents fixed-point numbers as intervals to track rounding information, ensuring correctness during arithmetic operations.
• Defines floating-point formats analogous to IEEE-754, with significands encoded in the RN-canonical form (2’s complement + round-bit).
• Performs addition and subtraction by splitting into 'near' and 'far' cases, using interval arithmetic to preserve rounding semantics.
• Applies standard 2’s complement arithmetic for multiplication and division, with minimal modifications to carry rounding information.
• Realizes directed roundings using a sticky-bit and conditional round-bit updates: RU sets r=1, RD sets r=0, RZ sets r=s_a, RA sets r=¬s_a, based on tail non-zero status.

Experimental results

Research questions

• RQ1 Can round-to-nearest rounding be achieved in constant time without log-time incrementation in floating-point arithmetic?
• RQ2 How can a signed-digit representation be encoded efficiently to support constant-time negation and rounding via truncation?
• RQ3 To what extent can standard 2’s complement arithmetic be reused in RN-represented arithmetic with minimal modification?
• RQ4 Can directed roundings be implemented efficiently in this representation without requiring rounding incrementation?
• RQ5 Does the RN-representation maintain precision equivalent to IEEE-754 while reducing hardware complexity and delay?

Key findings

• Rounding to nearest is achieved in constant time via truncation of the RN-canonical representation, eliminating the need for log-time incrementation in IEEE-754.
• Negation is performed in constant time via bit-wise inversion, a significant improvement over standard 2’s complement which requires a full adder.
• Addition and subtraction operations are implemented with minimal changes to standard 2’s complement logic, leveraging interval-based semantics for correctness.
• Multiplication and division are defined using standard algorithms adapted to carry rounding information, with no additional cost beyond standard 2’s complement operations.
• Directed roundings (RU, RD, RZ, RA) are realizable using a sticky-bit and conditional round-bit updates, without requiring incrementation.
• The RN-representation achieves the same discretization error and precision as IEEE-754 in the same format, but with reduced area and delay in hardware implementations.