[Paper Review] FPGA Implementation of $\mathbb{F}_2$-Linear Pseudorandom Number Generators Based on Zynq MPSoC: a Chaotic Iterations Post Processing Case Study

Mohammed Bakiri, Jean-François Couchot+1 more|arXiv (Cornell University)|Nov 25, 2016

Chaos-based Image/Signal Encryption22 references4 citations

TL;DR

This paper presents an FPGA-based hardware implementation of 18 $Δ}_2$-linear pseudorandom number generators (PRNGs) using Zynq MPSoC, comparing RTL and High-Level Synthesis (HLS) flows. It demonstrates that chaotic iterations as a post-processing technique significantly improve statistical quality, enabling PRNGs that previously failed the TestU01 battery to pass the stringent Big-Crush suite, with optimized combinations achieving high throughput and low resource usage without DSP or RAM blocks.

ABSTRACT

Pseudorandom number generation (PRNG) is a key element in hardware security platforms like field-programmable gate array FPGA circuits. In this article, 18 PRNGs belonging in 4 families (xorshift, LFSR, TGFSR, and LCG) are physically implemented in a FPGA and compared in terms of area, throughput, and statistical tests. Two flows of conception are used for Register Transfer Level (RTL) and High-level Synthesis (HLS). Additionally, the relations between linear complexity, seeds, and arithmetic operations on the one hand, and the resources deployed in FPGA on the other hand, are deeply investigated. In order to do that, a SoC based on Zynq EPP with ARM Cortex-$A9$ MPSoC is developed to accelerate the implementation and the tests of various PRNGs on FPGA hardware. A case study is finally proposed using chaotic iterations as a post processing for FPGA. The latter has improved the statistical profile of a combination of PRNGs that, without it, failed in the so-called TestU01 statistical battery of tests.

Motivation & Objective

• To evaluate and compare the hardware performance of 18 $Δ}_2$-linear PRNGs (xorshift, LFSR, TGFSR, LCG) in FPGA using RTL and HLS flows.
• To investigate the impact of linear complexity, seed size, and arithmetic operations on FPGA resource utilization and throughput.
• To develop a Zynq-based MPSoC platform for accelerated hardware prototyping and testing of PRNGs.
• To assess the effectiveness of chaotic iterations as a post-processing technique in enhancing the statistical quality of flawed PRNGs.
• To identify optimal PRNG combinations and chaotic iteration parameters for achieving high performance, low area, and strong statistical properties.

Proposed method

• Implement 18 PRNGs from four families (xorshift, LFSR, TGFSR, LCG) using both RTL and HLS flows on a Zynq MPSoC platform.
• Design a System-on-Chip (SoC) with ARM Cortex-A9 and programmable logic to accelerate PRNG implementation and testing.
• Apply chaotic iterations (CIs) as a post-processing technique using a modified strategy based on three PRNGs to generate dynamic selection sets.
• Use the negation function $f(x) = \overline{x}$ in CIs, with subset selection driven by outputs from three PRNGs to update state bits.
• Implement a hardware-efficient CI-based PRNG (XOR-CIPRNG) using bit-level operations and masking, selecting only the $\log(\log(n))$ least significant bits for output.
• Evaluate all configurations using the TestU01 statistical test battery, particularly the Big-Crush suite, to assess statistical quality.

Experimental results

Research questions

• RQ1 How do different PRNG families (xorshift, LFSR, TGFSR, LCG) compare in terms of area, throughput, and statistical quality when implemented on FPGA using RTL and HLS flows?
• RQ2 What is the relationship between linear complexity, seed size, and arithmetic operations in determining FPGA resource usage and performance of PRNGs?
• RQ3 Can chaotic iterations effectively improve the statistical profile of PRNGs that fail standard statistical tests?
• RQ4 Which combinations of PRNGs and chaotic iteration parameters yield optimal trade-offs between area, throughput, and statistical quality?
• RQ5 Can a hardware post-processor based on chaotic iterations enable high-performance, low-area PRNGs without relying on DSP or RAM blocks?

Key findings

• The xorshift64 and LFSR113 generators achieved the best hardware performance in terms of area and throughput across all tested PRNGs.
• The PCG32 and xorshift* PRNGs showed superior statistical quality, passing the entire TestU01 battery, including the most stringent Big-Crush suite.
• Chaotic iterations post-processing successfully enabled all tested PRNG combinations to pass the Big-Crush statistical test battery, even when the original generators failed.
• Specific combinations such as [xorshift64, xorshift+, LFSR113] and [xorshift+, xorshift+, Taus88] achieved throughput of 5.5–6.9 Gbps with area under 7.8×10³ slices, outperforming MRG32k3a without using DSP or RAM blocks.
• The implementation of chaotic iterations required minimal additional resources: only 0–8 RAM blocks and 0–6 DSPs, with area ranging from 6.58×10³ to 11.2×10³ slices depending on the PRNG combination.
• The use of only 3 least significant bits from the chaotic strategy ensured sufficient pseudorandomness while maintaining low hardware cost.