[Paper Review] Hardware-based Security for Virtual Trusted Platform Modules

Sami Alsouri, Thomas Feller+2 more|arXiv (Cornell University)|Aug 7, 2013

Security and Verification in Computing12 references3 citations

TL;DR

This paper proposes two hardware-based security mechanisms—hash tree and incremental hashing—to bind virtual PCRs (vPCRs) to physical hardware PCRs in virtualized environments, ensuring resistance to software attacks. The approach achieves O(log n) update complexity with FPGA-based implementations showing low overhead, preserving the trustworthiness of virtual TPMs without expanding the trusted computing base.

ABSTRACT

Virtual Trusted Platform modules (TPMs) were proposed as a software-based alternative to the hardware-based TPMs to allow the use of their cryptographic functionalities in scenarios where multiple TPMs are required in a single platform, such as in virtualized environments. However, virtualizing TPMs, especially virutalizing the Platform Configuration Registers (PCRs), strikes against one of the core principles of Trusted Computing, namely the need for a hardware-based root of trust. In this paper we show how strength of hardware-based security can be gained in virtual PCRs by binding them to their corresponding hardware PCRs. We propose two approaches for such a binding. For this purpose, the first variant uses binary hash trees, whereas the other variant uses incremental hashing. In addition, we present an FPGA-based implementation of both variants and evaluate their performance.

Motivation & Objective

• To address the security vulnerability of software-based virtual TPMs (vTPMs), which lack hardware-based trust and expand the trusted computing base (TCB).
• To restore hardware-level security to virtual PCRs by binding them to a single physical hardware PCR.
• To reduce the TCB in virtualized environments by ensuring vPCR integrity is cryptographically anchored to a trusted hardware root.
• To evaluate practical feasibility through FPGA implementations of two novel binding techniques: binary hash trees and incremental hashing.

Proposed method

• Uses binary hash trees to combine multiple vPCRs of the same index into a single root hash, stored in a hardware PCR, ensuring integrity through cryptographic hashing.
• Employs incremental hashing to maintain an aggregated hash of vPCR values, enabling efficient updates via modular arithmetic operations.
• Implements both schemes on a Virtex5 FPGA platform to evaluate performance and resource usage under real-world constraints.
• Proposes extensions to the TPM specification to support native hash tree and incremental hashing operations, as current TPMs lack such interfaces.
• Designs the hash computation to be performed inside the TPM to prevent tampering and ensure trust in the result.
• Introduces a history-tracking mechanism in incremental hashing to prevent malicious reset attacks, preserving auditability.

Experimental results

Research questions

• RQ1 Can virtual PCRs be securely bound to a hardware PCR to restore hardware-based trust in virtualized environments?
• RQ2 How do the computational and resource overheads of hash tree-based and incremental hashing-based binding schemes compare in practice?
• RQ3 What performance characteristics (update and verification times) do these schemes achieve on an FPGA platform?
• RQ4 Can the proposed binding mechanisms be implemented within existing TPM constraints, or do they require specification extensions?
• RQ5 How does the verification complexity scale with the number of virtual TPMs and update operations?

Key findings

• The hash tree-based binding achieves O(log n) complexity for both update and verification operations, with a measured update time of 1.4 μs on the FPGA.
• The incremental hashing-based binding offers O(1) update complexity but suffers from O(n*u) verification complexity, resulting in a 55.4 μs verification time—over 30 times slower than the hash tree approach.
• The hash tree implementation shows a 20% performance gain from parallel SHA-1 computation, but communication overhead via the LPC bus remains the dominant bottleneck.
• Resource consumption for the incremental hashing scheme is significant: 14,371 LUTs and 6,175 registers for the shift-and-add multiplier alone.
• The incremental hashing approach requires storing update history to prevent reset attacks, which increases verification complexity and limits scalability.
• Both approaches are feasible with reasonable overhead, and the authors propose specification extensions to support these mechanisms in future TPMs.