[Paper Review] Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities

Mohammad Hosseinabady, Mohd Amiruddin Zainol+1 more|arXiv (Cornell University)|Jan 18, 2019

Parallel Computing and Optimization Techniques22 references4 citations

TL;DR

This paper proposes a heterogeneous FPGA+GPU embedded system to optimize performance and energy efficiency in edge computing. It introduces a stream computing framework for FPGA acceleration, a performance/power modeling technique, and a dynamic task-scheduling strategy, achieving 1.79x speedup and 2.29x improvement in energy efficiency across image histogram, dense, and sparse matrix-vector multiplication workloads when both accelerators execute in parallel.

ABSTRACT

The edge computing paradigm has emerged to handle cloud computing issues such as scalability, security and low response time among others. This new computing trend heavily relies on ubiquitous embedded systems on the edge. Performance and energy consumption are two main factors that should be considered during the design of such systems. Focusing on performance and energy consumption, this paper studies the opportunities and challenges that a heterogeneous embedded system consisting of embedded FPGAs and GPUs (as accelerators) can provide for applications. We study three design, modeling and scheduling challenges throughout the paper. We also propose three techniques to cope with these three challenges. Applying the proposed techniques to three applications including image histogram, dense matrix-vector multiplication and sparse matrix-vector multiplications show 1.79x and 2.29x improvements in performance and energy consumption, respectively, when both FPGA and GPU execute the corresponding application in parallel.

Motivation & Objective

• Address the growing need for high-performance, low-energy edge computing in IoT and embedded systems.
• Overcome the challenges of designing, modeling, and scheduling heterogeneous FPGA+GPU systems for optimal performance and energy efficiency.
• Develop a systematic methodology to enable efficient task offloading between embedded FPGAs and GPUs.
• Demonstrate the benefits of collaborative execution on real-world workloads such as image processing and sparse/dense matrix operations.

Proposed method

• Propose a stream computing engine using high-level synthesis (HLS) tools to map diverse applications efficiently onto embedded FPGAs.
• Develop a performance and power modeling technique to predict execution characteristics of FPGA and GPU workloads.
• Design a dynamic task-scheduling algorithm that divides workloads between FPGA and GPU based on data size and platform capabilities.
• Implement and evaluate the framework on three applications: image histogram, dense matrix-vector multiplication (DeMV), and sparse matrix-vector multiplication (SpMV).
• Use zero-copy memory access via shared address space to eliminate PCIe overhead and improve memory bandwidth utilization.
• Apply loop unrolling and pipelining techniques in FPGA designs to achieve high throughput and low initiation interval (II=1).

Experimental results

Research questions

• RQ1 How can a heterogeneous FPGA+GPU embedded system achieve better performance and energy efficiency than standalone accelerators?
• RQ2 What systematic design methodology enables efficient FPGA acceleration of diverse workloads using HLS tools?
• RQ3 How can performance and energy consumption be accurately modeled for FPGA and GPU components in a shared-memory embedded system?
• RQ4 What scheduling strategy optimally divides a parallel task between FPGA and GPU to minimize execution time and energy consumption?

Key findings

• The proposed FPGA+GPU collaboration achieves a 1.79x improvement in performance and a 2.29x improvement in energy efficiency compared to GPU-only execution.
• For the image histogram workload, the Zynq MPSoC FPGA consumes significantly less power (up to 5.2x less) than the Jetson TX1 GPU.
• The DeMV application shows a 1.48x performance gain and 1.19x energy efficiency improvement when the task is split between Zynq and Jetson compared to GPU-only execution.
• The SpMV workload achieves a 3.2x speedup on Jetson relative to Zynq MPSoC for large data sizes, with 1.46x performance and 1.23x energy efficiency gains when using both FPGA and GPU.
• The FPGA-based design achieves II=1 after loop unrolling, enabling maximum throughput and eliminating pipeline bottlenecks.
• The shared memory architecture with zero-copy access reduces inter-processor communication overhead and improves memory bandwidth utilization.