[Paper Review] High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning

Songming Yu, Yongpan Liu+6 more|arXiv (Cornell University)|Oct 13, 2020

Advanced Memory and Neural Computing20 references4 citations

TL;DR

This paper proposes a high-area and energy-efficient RRAM-based CNN accelerator using a novel kernel-reordering weight mapping scheme based on pattern pruning. By exploiting structured sparsity through pattern pruning and leveraging the Operation Unit (OU) mechanism, the design achieves up to 5.20x crossbar area efficiency, 2.15x energy efficiency, and 1.35x performance speedup over baseline methods with minimal accuracy loss.

ABSTRACT

Resistive Random Access Memory (RRAM) is an emerging device for processing-in-memory (PIM) architecture to accelerate convolutional neural network (CNN). However, due to the highly coupled crossbar structure in the RRAM array, it is difficult to exploit the sparsity of the network in RRAM-based CNN accelerator. To optimize the weight mapping of sparse network in the RRAM array and achieve high area and energy efficiency, we propose a novel weight mapping scheme and corresponding RRAM-based CNN accelerator architecture based on pattern pruning and Operation Unit(OU) mechanism. Experimental results show that our work can achieve 4.16x-5.20x crossbar area efficiency, 1.98x-2.15x energy efficiency, and 1.15x-1.35x performance speedup in comparison with the traditional weight mapping method.

Motivation & Objective

• To address the challenge of low area and energy efficiency in RRAM-based CNN accelerators when handling sparse, irregularly structured weights.
• To exploit network sparsity effectively in RRAM crossbar arrays without sacrificing accuracy.
• To design a hardware-aware weight mapping scheme that supports both structured sparsity and efficient computation in RRAM-based PIM architectures.
• To achieve high performance, area, and energy efficiency by combining pattern pruning with an OU-based computation mechanism.

Proposed method

• Introduces a pattern pruning algorithm that creates structured, hardware-friendly sparsity patterns with up to 12 patterns per layer, enabling efficient mapping in RRAM crossbars.
• Develops a kernel-reordering weight mapping scheme that reorganizes filters within each input channel based on output channel index to group similar patterns and reduce crossbar utilization.
• Employs an Operation Unit (OU) mechanism to enable fine-grained activation of wordlines and bitlines, allowing selective computation on non-zero patterns only.
• Integrates an all-zero pattern detection module in the input preprocessing unit to skip unnecessary ADC/DAC conversions and reduce dynamic energy.
• Uses index storage for kernel output channel positions and pattern shapes to enable correct data routing without storing zero-weight patterns in RRAM.
• Designs a complete RRAM-based CNN accelerator architecture that supports the proposed mapping scheme and leverages both weight and feature map sparsity.

Experimental results

Research questions

• RQ1 How can structured sparsity from pattern pruning be effectively exploited in RRAM crossbar arrays to improve area and energy efficiency?
• RQ2 What is the impact of kernel-reordering and OU-based computation on crossbar utilization and energy consumption in sparse CNN inference?
• RQ3 Can pattern pruning achieve high sparsity with minimal accuracy loss while remaining compatible with RRAM-based PIM architectures?
• RQ4 How does the proposed mapping scheme compare to naive weight mapping in terms of area, energy, and performance efficiency?

Key findings

• The proposed pattern-pruned mapping scheme achieves 4.16x to 5.20x crossbar area efficiency improvement over the baseline method, saving 76.0% to 80.8% RRAM crossbar area.
• Energy efficiency is improved by 1.98x to 2.15x across CIFAR-10, CIFAR-100, and ImageNet datasets, with ADC energy being the main bottleneck.
• Performance speedup of 1.15x to 1.35x is achieved, primarily due to elimination of all-zero pattern computations and reduced memory access.
• Index overhead for kernel reordering is only 12.2% of the total model size (729.5KB–1013.5KB), which is acceptable compared to the compressed model size.
• The method achieves near-theoretical optimal area efficiency, with results close to the theoretical maximum (86.03% for CIFAR-10), indicating effective sparsity exploitation.
• The performance on ImageNet is relatively lower due to less favorable pattern pruning results, with lower sparsity and higher pattern count, leading to reduced mapping efficiency.