[Paper Review] High Speed and Area Efficient 2D DWT Processor based Image Compression" Signal & Image Processing

Sugreev Kaur, Rajesh Mehra|arXiv (Cornell University)|Jan 3, 2011

Advanced Data Compression Techniques4 references3 citations

TL;DR

This paper presents a high-speed, area-efficient 2D Discrete Wavelet Transform (DWT) processor for image compression using a pipelined partially serial architecture on FPGA. Implemented on Xilinx Spartan 3E (XC3S500E-4fg320), the design achieves 231 MHz operation with 117 mW power consumption, demonstrating a 15% speed improvement over prior work while reducing resource utilization.

ABSTRACT

This paper presents a high speed and area efficient DWT processor based design for Image Compression applications. In this proposed design, pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on target FPGA. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and implemented on Spartan 2 and 3 based XC2S100-5tq144 and XC3S500E-4fg320 target device. The results show that proposed design can operate at maximum frequency 231 MHz in case of Spartan 3 by consuming power of 117mW at 28 degree/c junction temperature. The result comparison has shown an improvement of 15% in speed.

Motivation & Objective

• To address the need for high-performance, low-power image compression in real-time multimedia and internet applications.
• To overcome the limitations of DCT-based compression, such as blocking artifacts and poor subjective quality at high compression ratios.
• To design a DWT processor that offers better image quality and computational efficiency than traditional DCT methods.
• To optimize hardware resource usage and throughput for real-time image processing on FPGA platforms.
• To achieve high-speed operation with minimal power consumption using pipelined, partially serial architecture on modern FPGAs.

Proposed method

• A pipelined partially serial architecture is employed to enhance throughput and reduce resource usage.
• The 2D DWT is implemented using a separable approach: 1D DWT is applied first along rows, then along columns.
• The design uses lifting-based DWT with Haar wavelet filters for efficient computation and reduced hardware complexity.
• The system is modeled in Simulink using System Generator blocks and synthesized using Xilinx Synthesis Tool (XST).
• The design is implemented on both Spartan 2 (XC2S100-5tq144) and Spartan 3E (XC3S500E-4fg320) FPGAs for performance and resource comparison.
• Power consumption is estimated using XPower utility, and timing analysis is performed to determine maximum operating frequency.

Experimental results

Research questions

• RQ1 Can a pipelined, partially serial DWT architecture achieve higher speed and better area efficiency than existing designs?
• RQ2 How does the performance of the proposed DWT processor compare to prior FPGA-based implementations in terms of maximum operating frequency and resource utilization?
• RQ3 What is the power consumption of the proposed DWT processor at 28°C junction temperature?
• RQ4 Does the use of a modern FPGA (Spartan 3E) enable significant performance gains over older FPGA platforms (Spartan 2)?
• RQ5 To what extent does the proposed design reduce blocking artifacts and improve image quality at high compression ratios compared to DCT-based methods?

Key findings

• The proposed DWT processor achieves a maximum operating frequency of 231.26 MHz when implemented on the Spartan 3E-based XC3S500E-4fg320 FPGA.
• The design consumes only 117 mW of power at a 28°C junction temperature, demonstrating low power consumption.
• Resource utilization is significantly reduced, with only 272 slices, 498 flip-flops, and 334 LUTs used on the Spartan 3E device.
• The design shows a 15% improvement in speed compared to the reference design from [8], which operated at 201.092 MHz on a Virtex-II FPGA.
• The Spartan 3E-based implementation uses only 5% of available slices, compared to 23% on the Spartan 2 device, indicating superior area efficiency.
• The timing analysis confirms a minimum period of 4.324 ns, enabling high-throughput image processing suitable for real-time applications.