[Paper Review] hlslib: Software Engineering for Hardware Design

Johannes de Fine Licht, Torsten Hoefler|arXiv (Cornell University)|Oct 10, 2019

Embedded Systems Design Techniques9 references17 citations

TL;DR

hlslib is an open-source C++ library that enhances high-level synthesis (HLS) development for FPGAs by providing portable CMake integration, unified OpenCL host code abstractions, and hardware-optimized C++ templates for FIFOs, shift registers, and tree reductions. It improves productivity and portability across Xilinx and Intel HLS tools by enabling hardware-aware abstractions and reusable, vendor-agnostic code patterns.

ABSTRACT

High-level synthesis (HLS) tools have brought FPGA development into the mainstream, by allowing programmers to design architectures using familiar languages such as C, C++, and OpenCL. While the move to these languages has brought significant benefits, many aspects of traditional software engineering are still unsupported, or not exploited by developers in practice. Furthermore, designing reconfigurable architectures requires support for hardware constructs, such as FIFOs and shift registers, that are not native to CPU-oriented languages. To address this gap, we have developed hlslib, a collection of software tools, plug-in hardware modules, and code samples, designed to enhance the productivity of HLS developers. The goal of hlslib is two-fold: first, create a community-driven arena of bleeding edge development, which can move quicker, and provides more powerful abstractions than what is provided by vendors; and second, collect a wide range of example codes, both minimal proofs of concept, and larger, real-world applications, that can be reused directly or inspire other work. hlslib is offered as an open source library, containing CMake files, C++ headers, convenience scripts, and examples codes, and is receptive to any contribution that can benefit HLS developers, through general functionality or examples.

Motivation & Objective

• Address the productivity gap in FPGA development by bridging traditional software engineering practices with hardware-aware abstractions.
• Reduce the complexity and portability issues in HLS workflows caused by vendor-specific toolchains and manual build configurations.
• Provide reusable, high-level hardware constructs (e.g., shift registers, tree reductions) that are otherwise difficult or error-prone to implement manually in HLS.
• Enable cross-vendor compatibility between Xilinx and Intel HLS tools through abstraction layers and consistent interfaces.
• Foster community-driven development by offering an open-source platform for sharing reusable code, examples, and hardware-optimized patterns.

Proposed method

• Integrate CMake via custom Find modules (FindSDAccel.cmake and FindIntelFPGAOpenCL.cmake) to manage build configurations and dependencies portably across platforms.
• Abstract low-level differences between Xilinx and Intel OpenCL APIs using a unified OpenCL wrapper that handles command queues, memory flags, and memory bank specifications.
• Implement templated hardware abstractions such as hlslib::ShiftRegister, which explicitly instantiate buffer partitions for shift register taps at compile time.
• Use variadic templates to express full hardware pipelines for tree reductions, ensuring balanced binary tree structures are synthesized correctly by HLS tools.
• Expose reusable, vendor-agnostic C++ components (e.g., Stream, DataPack) that map efficiently to hardware resources and support pipelining and streaming.
• Provide example codes and integration patterns for real-world use, including support for frameworks like DaCe and SMI, to demonstrate end-to-end usability.

Experimental results

Research questions

• RQ1 How can high-level synthesis (HLS) workflows be made more portable and maintainable across different FPGA toolchains like Xilinx Vivado HLS and Intel OpenCL?
• RQ2 To what extent can high-level software engineering practices—such as build automation, dependency management, and abstraction—be effectively applied to HLS development?
• RQ3 Can reusable, hardware-optimized C++ abstractions (e.g., shift registers, tree reductions) be implemented in a way that is both portable and efficiently synthesized by HLS tools?
• RQ4 How can differences between Xilinx and Intel OpenCL APIs be abstracted to enable a single, unified host codebase for FPGA kernels?
• RQ5 What impact do high-level abstractions have on the maintainability, correctness, and performance of HLS-generated hardware designs?

Key findings

• hlslib enables cross-vendor compatibility by abstracting differences in OpenCL command queues, memory flags, and memory bank specifications between Xilinx and Intel FPGA toolchains.
• The use of CMake integration with vendor-specific Find modules significantly improves project portability and reduces configuration overhead compared to manual makefiles.
• hlslib's templated ShiftRegister abstraction allows explicit, compile-time instantiation of shift register taps, ensuring correct buffer partitioning and avoiding reliance on pattern recognition by HLS tools.
• The TreeReduce template ensures fully pipelined, balanced binary tree reductions by explicitly instantiating the tree structure, which avoids incorrect optimizations or unrolling by HLS compilers.
• hlslib's abstractions are production-ready and already integrated into real-world projects such as DaCe and the Streaming Message Interface (SMI), demonstrating practical utility and community adoption.
• By providing reusable, well-documented examples and a community-driven development model, hlslib accelerates the adoption of best practices in HLS development beyond what is natively supported by vendor tools.