[Paper Review] IPA in the Loop: Control Design for Throughput Regulation in Computer Processors

Xinwei Chen, Y. Wardi+1 more|arXiv (Cornell University)|Apr 10, 2016

Parallel Computing and Optimization Techniques12 references3 citations

TL;DR

This paper presents an IPA-based adaptive integral control law for real-time throughput regulation in multicore processors, using Infinitesimal Perturbation Analysis (IPA) to estimate gradient feedback and adjust control gain dynamically. Implemented on an Intel Haswell processor, the method achieves better performance than in cycle-level simulation, with average throughput offsets within ±30 MIPS of target rates across multiple configurations.

ABSTRACT

A new technique for performance regulation in event-driven systems, recently proposed by the authors, consists of an adaptive-gain integral control. The gain is adjusted in the control loop by a real-time estimation of the derivative of the plant-function with respect to the control input. This estimation is carried out by Infinitesimal Perturbation Analysis (IPA). The main motivation comes from applications to throughput regulation in computer processors, where to-date, testing and assessment of the proposed control technique has been assessed by simulation. The purpose of this paper is to report on its implementation on a machine, namely an Intel Haswell microprocessor, and compare its performance to that obtained from cycle-level, full system simulation environment. The intrinsic contribution of the paper to the Workshop on Discrete Event System is in describing the process of taking an IPA-based design and simulation to a concrete implementation, thereby providing a bridge between theory and applications.

Motivation & Objective

• To bridge theoretical control design with real-world implementation in event-driven systems, particularly for throughput regulation in computer processors.
• To evaluate the performance of an IPA-based adaptive integral control law in a physical hardware environment, contrasting it with cycle-level simulation.
• To demonstrate the feasibility and robustness of low-complexity, real-time control using IPA-derived gradient estimates in a multicore processor setting.
• To validate that the control technique maintains stability and accuracy despite computational approximations in real-world deployment.

Proposed method

• The control law uses a discrete-time integrator with adaptive gain $ A_n $, updated via the inverse of the IPA-estimated derivative $ L_n'(u_n) $, which quantifies the sensitivity of throughput to clock frequency.
• The plant model represents a multicore processor as a discrete-event system, with throughput $ y_n $ computed as instructions per cycle over control cycles $ C_n $.
• IPA is applied to estimate $ \partial y_n / \partial u_n $ along sample paths using low-cost, path-based rules, enabling real-time gradient computation without unbiasedness.
• The control loop recursively updates the clock frequency $ u_n $ using $ u_n = u_{n-1} + A_n e_{n-1} $, where $ e_n = r - y_n $ is the error from the target throughput $ r $.
• The system is implemented on an Intel Haswell processor, with throughput and clock frequency monitored over time for different workloads (Barnes, Water-ns).
• The control cycle length is determined by instruction batches, and throughput is computed as $ N / d_N(\tau) $, where $ d_N $ is the departure time of the last instruction.

Experimental results

Research questions

• RQ1 Can an IPA-based adaptive integral control law achieve stable and accurate throughput regulation in a real multicore processor?
• RQ2 How does the performance of the IPA-in-the-loop control technique compare between hardware implementation and cycle-level simulation?
• RQ3 Does the use of biased but low-complexity IPA derivatives still yield robust and accurate control in real-time systems?
• RQ4 What is the impact of system-level factors such as core-level vs. aggregate throughput regulation on control performance?

Key findings

• The hardware implementation on the Intel Haswell processor achieved better regulation performance than in the Manifold cycle-level simulation environment.
• For a target throughput of 1,200 MIPS, the Barnes workload showed an average throughput offset of -33.5 MIPS on hardware, compared to a larger offset in simulation.
• The Water-ns workload exhibited a -56.8 MIPS offset at 1,200 MIPS target on hardware, indicating higher deviation but still within acceptable bounds for real-time control.
• Across all tested targets (1,200, 1,000, 800 MIPS), the hardware implementation consistently showed smaller or comparable offsets than simulation, indicating robustness to real-world approximations.
• The control system maintained stability and convergence despite crude approximations in the implementation, validating the low-complexity design principle.
• The results confirm that IPA-based gradient estimation, even when biased, supports effective real-time control with minimal computational overhead.