[Paper Review] LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation

Ruizhe Zhong, Xingbo Du+8 more|arXiv (Cornell University)|Dec 28, 2023

Machine Learning in Materials Science9 citations

TL;DR

A systematic survey of how large language models can assist EDA, covering assistant chatbots, HDL/script generation, and HDL verification/analysis, with datasets and backbones used, and future directions in logic synthesis, physical design, and multi-modal integration.

ABSTRACT

Driven by Moore's Law, the complexity and scale of modern chip design are increasing rapidly. Electronic Design Automation (EDA) has been widely applied to address the challenges encountered in the full chip design process. However, the evolution of very large-scale integrated circuits has made chip design time-consuming and resource-intensive, requiring substantial prior expert knowledge. Additionally, intermediate human control activities are crucial for seeking optimal solutions. In system design stage, circuits are usually represented with Hardware Description Language (HDL) as a textual format. Recently, Large Language Models (LLMs) have demonstrated their capability in context understanding, logic reasoning and answer generation. Since circuit can be represented with HDL in a textual format, it is reasonable to question whether LLMs can be leveraged in the EDA field to achieve fully automated chip design and generate circuits with improved power, performance, and area (PPA). In this paper, we present a systematic study on the application of LLMs in the EDA field, categorizing it into the following cases: 1) assistant chatbot, 2) HDL and script generation, and 3) HDL verification and analysis. Additionally, we highlight the future research direction, focusing on applying LLMs in logic synthesis, physical design, multi-modal feature extraction and alignment of circuits. We collect relevant papers up-to-date in this field via the following link: https://github.com/Thinklab-SJTU/Awesome-LLM4EDA.

Motivation & Objective

• Motivate automation of chip design under growing EDA complexity and PPA constraints using LLMs.
• Categorize current LLM applications in EDA into assistant chatbot, HDL/script generation, and HDL verification/analysis.
• Summarize datasets, model backbones, and fine-tuning strategies used for LLM4EDA.
• Highlight challenges and future directions including logic synthesis, physical design, and multi-modal circuit alignment.

Proposed method

• Survey and taxonomy of LLM4EDA applications with representative works and systematization.
• Compilation of datasets and backbones used for domain-specific fine-tuning of LLMs in EDA.
• Discussion of evaluation metrics for HDL generation (syntax, functionality, PPA) and verification/analysis.
• Synthesis of architectural trends, prompts, and data sources across HDL generation and verification workflows.
• Proposed directions for multi-modal circuit modeling and long-chain PPA feedback in EDA.

Experimental results

Research questions

• RQ1 What are the main ways LLMs are being applied in EDA (assistant chatbot, HDL/script generation, HDL verification/analysis)?
• RQ2 What datasets, model backbones, and fine-tuning strategies have enabled progress in LLM4EDA?
• RQ3 How are HDL generation and verification evaluated, and what are the gaps in current evaluation frameworks?
• RQ4 What future directions (logic synthesis, physical design, multi-modal data, PPA feedback) are promising for LLMs in EDA?

Key findings

• LLMs have been explored as assistant chatbots, HDL/code generation tools, and HDL verification/analysis assistants in EDA.
• Domain-specific datasets and fine-tuning (e.g., instruction tuning, SFT, QLoRA) enable better LLM performance for EDA tasks.
• Evaluation frameworks consider syntax, functionality, and design quality (PPA) for generated HDL/code, with benchmarks like pass@k used in RTL generation.
• Multiple backbones (LLaMA2, GPT-3.5/4, GPT-4 variants) and fine-tuning approaches have been applied to HDL-related tasks.
• Future directions include integrating LLMs into logic synthesis and physical design, and building multi-modal, circuit-aligned pre-trained models.