[Paper Review] Lord of the Ring(s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical

Riccardo Paccagnella, Licheng Luo+1 more|arXiv (Cornell University)|Mar 5, 2021

Security and Verification in Computing89 references25 citations

TL;DR

This paper demonstrates practical on-chip cross-core side channels using the CPU ring interconnect, building a covert channel up to 4.14 Mbps and leaking cryptographic keys and keystroke timing.

ABSTRACT

We introduce the first microarchitectural side channel attacks that leverage contention on the CPU ring interconnect. There are two challenges that make it uniquely difficult to exploit this channel. First, little is known about the ring interconnect's functioning and architecture. Second, information that can be learned by an attacker through ring contention is noisy by nature and has coarse spatial granularity. To address the first challenge, we perform a thorough reverse engineering of the sophisticated protocols that handle communication on the ring interconnect. With this knowledge, we build a cross-core covert channel over the ring interconnect with a capacity of over 4 Mbps from a single thread, the largest to date for a cross-core channel not relying on shared memory. To address the second challenge, we leverage the fine-grained temporal patterns of ring contention to infer a victim program's secrets. We demonstrate our attack by extracting key bits from vulnerable EdDSA and RSA implementations, as well as inferring the precise timing of keystrokes typed by a victim user.

Motivation & Objective

• Motivate and exploit a previously under-studied on-chip communication channel (the ring interconnect) to enable covert channels and side channels.
• Reverse engineer Intel’s ring protocol to understand resources and contention behavior on the ring interconnect.
• Show practical attacks that extract cryptographic key bits and keystroke timing from a victim.
• Demonstrate countermeasures and discuss mitigations for ring-based leakage.

Proposed method

• Perform thorough reverse engineering of Intel's ring interconnect protocols to map ring resources and arbitration behavior.
• Construct a cross-core covert channel over the ring interconnect with a single thread, achieving up to 4.14 Mbps (518 KBps).
• Characterize ring topology, lanes, and contention conditions through empirical measurements on Coffee Lake and Skylake CPUs.
• Design and execute ring-contention based side-channel attacks that extract key bits from RSA and EdDSA implementations and infer keystroke timings.
• Use timing traces and machine learning to de-noise and recover secrets from ring contention signals.

Experimental results

Research questions

• RQ1 What are the necessary and sufficient conditions for contention on the CPU ring interconnect between processes?
• RQ2 Can ring contention be leveraged to create a cross-core covert channel without shared memory?
• RQ3 Can ring contention leaks be exploited to recover cryptographic keys from RSA and EdDSA implementations?
• RQ4 Can keystroke timing information be inferred from ring contention patterns?
• RQ5 What mitigations effectively reduce or prevent ring-based side channels?

Key findings

• The ring interconnect topology comprises two independent lanes with four sub-rings servicing different packet types.
• A cross-core covert channel with a single thread achieving up to 4.14 Mbps (518 KBps) is demonstrated without shared memory.
• Ring contention signals correlate with victim loads and can be used to infer private information under adversarial scheduling.
• Contention occurs under specific conditions when sender and receiver traffic travel in the same direction through overlapping ring segments and priority rules apply.
• Keystroke timing can be inferred from spikes in ring contention, enabling timing-based leakage.
• The authors provide a structured formalization of contention conditions and observed ring behaviors that explain when attacks succeed.