[Paper Review] Massive MIMO with Arbitrary Non-Ideal Arrays: Hardware Scaling Laws and Circuit-Aware Design

Emil Björnson, Michail Matthaiou+1 more|arXiv (Cornell University)|Jan 1, 2014

Advanced MIMO Systems Optimization13 citations

TL;DR

This paper establishes hardware scaling laws for massive MIMO systems with arbitrary, non-ideal antenna arrays, proving that user rates remain robust despite hardware impairments like phase drift and additive distortion. It demonstrates that circuit power can scale as √N instead of linearly with N through circuit-aware design, enabling cost-efficient deployment of large-scale arrays.

ABSTRACT

Massive multiple-input multiple-output (MIMO) systems are cellular networks where the base stations (BSs) are equipped with unconventionally many antennas, deployed on co-located or distributed arrays. Huge spatial degrees-of-freedom are achieved by coherent processing over these massive arrays, which provide strong signal gains, resilience to imperfect channel knowledge, and low interference. This comes at the price of more infrastructure; the hardware cost and circuit power consumption scale linearly/affinely with the number of BS antennas $N$. Hence, the key to cost-efficient deployment of large arrays is low-cost antenna branches with low circuit power, in contrast to today's conventional expensive and power-hungry BS antenna branches. Such low-cost transceivers are prone to hardware imperfections, but it has been conjectured that the huge degrees-of-freedom would bring robustness to such imperfections. We prove this claim for a generalized uplink system with multiplicative phase-drifts, additive distortion noise, and noise amplification. Specifically, we derive closed-form expressions for the user rates and a scaling law that shows how fast the hardware imperfections can increase with $N$ while maintaining high rates. The connection between this scaling law and the power consumption of different transceiver circuits is rigorously exemplified. This reveals that one can make the circuit power increase as $\sqrt{N}$, instead of linearly, by careful circuit-aware system design.

Motivation & Objective

• To investigate the impact of hardware impairments—such as phase drift, additive distortion, and noise amplification—on massive MIMO systems with arbitrary, non-ideal arrays.
• To determine the fundamental trade-off between hardware imperfections and system performance in uplink massive MIMO.
• To derive scaling laws that quantify how fast hardware impairments can grow with the number of antennas N while maintaining high spectral efficiency.
• To connect these scaling laws to actual circuit power consumption and enable low-power, cost-effective transceiver designs.

Proposed method

• Derives closed-form expressions for user rates in a generalized uplink massive MIMO system with multiplicative phase-drifts and additive distortion noise.
• Analyzes the system under coherent processing over massive arrays to exploit spatial degrees of freedom and mitigate channel uncertainty.
• Establishes a scaling law showing that hardware impairments can grow proportionally to √N while maintaining high spectral efficiency.
• Links the derived scaling law to the power consumption of different transceiver circuits, enabling circuit-aware system design.
• Uses mathematical analysis to prove that circuit power can scale as √N instead of linearly with N by optimizing hardware design.
• Considers a realistic model including noise amplification and non-ideal components to reflect practical deployment constraints.

Experimental results

Research questions

• RQ1 How do hardware impairments such as phase drift and additive distortion affect user rates in massive MIMO systems with arbitrary, non-ideal arrays?
• RQ2 What is the maximum rate at which hardware imperfections can scale with the number of antennas N while maintaining high spectral efficiency?
• RQ3 Can circuit power consumption be reduced from linear to sub-linear scaling with N through intelligent system design?
• RQ4 What is the connection between the derived scaling law and the actual power consumption of transceiver circuits in massive MIMO systems?

Key findings

• Hardware impairments such as phase drift and additive distortion can scale as √N while maintaining high user rates, due to the large spatial degrees of freedom in massive MIMO.
• The system achieves robust performance against hardware imperfections, confirming the conjecture that massive arrays inherently mitigate non-ideal hardware effects.
• Circuit power consumption can be reduced from linear scaling (O(N)) to √N scaling (O(√N)) through circuit-aware system design.
• The derived scaling law provides a quantitative design guideline for balancing hardware quality and system cost in large-scale MIMO deployments.
• The closed-form rate expressions enable precise performance evaluation and optimization under realistic hardware constraints.
• The results demonstrate that low-cost, low-power transceivers are viable for massive MIMO when combined with proper system-level design.