[Paper Review] Modeling and visualizing networked multi-core embedded software energy consumption

Steve Kerrison, Kerstin Eder|arXiv (Cornell University)|Sep 9, 2015

Parallel Computing and Optimization Techniques13 references4 citations

TL;DR

This paper presents a parametric energy model for networked multi-core embedded systems based on the cache-less, timing-predictable XS1-L architecture, integrating voltage and frequency scaling (VFS) and enhanced instruction set simulation to enable accurate, visualizable energy estimation. The model achieves an average energy estimation error of ±5%, with a core model error of 2.67% and a network model error of -4.92%, supporting energy-aware software design decisions through simulation and visualization workflows.

ABSTRACT

In this report we present a network-level multi-core energy model and a software development process workflow that allows software developers to estimate the energy consumption of multi-core embedded programs. This work focuses on a high performance, cache-less and timing predictable embedded processor architecture, XS1. Prior modelling work is improved to increase accuracy, then extended to be parametric with respect to voltage and frequency scaling (VFS) and then integrated into a larger scale model of a network of interconnected cores. The modelling is supported by enhancements to an open source instruction set simulator to provide the first network timing aware simulations of the target architecture. Simulation based modelling techniques are combined with methods of results presentation to demonstrate how such work can be integrated into a software developer's workflow, enabling the developer to make informed, energy aware coding decisions. A set of single-, multi-threaded and multi-core benchmarks are used to exercise and evaluate the models and provide use case examples for how results can be presented and interpreted. The models all yield accuracy within an average +/-5 % error margin.

Motivation & Objective

• To address the lack of tools for estimating energy consumption in multi-core embedded software, particularly in systems with timing predictability and limited energy resources.
• To improve energy modeling accuracy by extending prior instruction-level profiling with regression trees and incorporating VFS parameters.
• To enhance the axe instruction set simulator with network timing awareness to support end-to-end simulation of multi-core communication and energy effects.
• To develop a visualization framework that enables developers to interpret energy consumption across cores and interconnects in real-time.
• To validate the model using multi-threaded and multi-core benchmarks, demonstrating usability in real-world design space exploration.

Proposed method

• Extends a prior single-core energy model using regression tree techniques to estimate energy for instructions not directly profiled.
• Integrates voltage and frequency scaling (VFS) into the energy model to support design space exploration across operating points.
• Enhances the open-source axe instruction set simulator with network-level timing modeling, including switch and link energy accounting.
• Employs simulation-based modeling using benchmarks to generate traces for energy estimation and visualization.
• Applies geometric mean and standard deviation metrics to evaluate model accuracy across multiple benchmarks.
• Visualizes energy consumption across cores, switches, and interconnects using color-coded representations for real-time insight.

Experimental results

Research questions

• RQ1 How can energy consumption in multi-core embedded software be accurately modeled when communication and synchronization are involved?
• RQ2 To what extent can VFS parameters be integrated into an energy model to support runtime and design-time optimization?
• RQ3 Can simulation-based energy modeling with enhanced instruction set simulation achieve sub-10% error margins in real-world embedded benchmarks?
• RQ4 How can energy consumption be effectively visualized across a network of cores to guide software development decisions?
• RQ5 What impact do thread allocation and communication patterns have on overall system energy consumption in multi-core embedded systems?

Key findings

• The single-core energy model achieves an average error of 2.67% with a standard deviation of 4.40%, significantly improving upon prior work.
• The network-capable energy model demonstrates an average error of -4.92% and a standard deviation of 3.92%, with a total error range of 15.72% across benchmarks.
• The VFS-aware model yields a mean squared error of 2.60%, indicating strong consistency in energy estimation across varying voltage and frequency settings.
• Simulation timing errors are within 3.10% on average, with energy model errors counterbalanced by timing over-prediction, highlighting the need for joint error analysis.
• Visualization of energy consumption reveals that poor thread allocation can increase network communication energy by up to three times, even with minimal timing impact.
• The model successfully identifies energy inefficiencies in single-core vs. dual-core configurations, demonstrating that workload distribution reduces core energy and leakage.