[Paper Review] Monolithic Silicon Photonic Architecture for Training Deep Neural Networks with Direct Feedback Alignment

Matthew J. Filipovich, Zhimu Guo+7 more|arXiv (Cornell University)|Nov 12, 2021

Neural Networks and Reservoir Computing40 references4 citations

TL;DR

This paper proposes a monolithic silicon photonic architecture for on-chip training of deep neural networks using direct feedback alignment, enabling trillions of MAC operations per second with sub-picojoule energy efficiency. The system uses microring resonator arrays to perform parallel, in-situ gradient computation during backpropagation, experimentally demonstrating training on MNIST with photonic MAC operations.

ABSTRACT

The field of artificial intelligence (AI) has witnessed tremendous growth in recent years, however some of the most pressing challenges for the continued development of AI systems are the fundamental bandwidth, energy efficiency, and speed limitations faced by electronic computer architectures. There has been growing interest in using photonic processors for performing neural network inference operations, however these networks are currently trained using standard digital electronics. Here, we propose on-chip training of neural networks enabled by a CMOS-compatible silicon photonic architecture to harness the potential for massively parallel, efficient, and fast data operations. Our scheme employs the direct feedback alignment training algorithm, which trains neural networks using error feedback rather than error backpropagation, and can operate at speeds of trillions of multiply-accumulate (MAC) operations per second while consuming less than one picojoule per MAC operation. The photonic architecture exploits parallelized matrix-vector multiplications using arrays of microring resonators for processing multi-channel analog signals along single waveguide buses to calculate the gradient vector of each neural network layer in situ, which is the most computationally expensive operation performed during the backward pass. We also experimentally demonstrate training a deep neural network with the MNIST dataset using on-chip MAC operation results. Our novel approach for efficient, ultra-fast neural network training showcases photonics as a promising platform for executing AI applications.

Motivation & Objective

• Address the growing demand for energy-efficient, high-speed AI hardware due to limitations in electronic architectures.
• Overcome the bottleneck of electronic training by integrating photonic processing for neural network training on-chip.
• Enable real-time, in-situ gradient computation during backpropagation using parallelized photonic MAC operations.
• Demonstrate the feasibility of training deep neural networks using only photonic hardware, minimizing reliance on digital electronics.

Proposed method

• Employ a CMOS-compatible silicon photonic platform to implement massively parallel, analog matrix-vector multiplication using arrays of microring resonators.
• Use single waveguide buses to transmit multi-channel analog signals, enabling efficient interconnection across the photonic processor.
• Implement the direct feedback alignment algorithm, which computes error feedback instead of backpropagating through error gradients.
• Perform in-situ gradient vector calculation for each neural network layer using photonic components, reducing computational latency.
• Integrate the photonic architecture to support both forward and backward passes of the network using the same hardware.
• Leverage the high bandwidth and low energy consumption of silicon photonics to achieve trillions of MAC operations per second.

Experimental results

Research questions

• RQ1 Can a monolithic silicon photonic architecture perform on-chip training of deep neural networks with sufficient speed and energy efficiency?
• RQ2 Can direct feedback alignment be effectively implemented in a photonic hardware platform to avoid backpropagation bottlenecks?
• RQ3 Can photonic MAC operations achieve the required precision and stability for end-to-end training of a deep neural network?
• RQ4 What is the energy and speed performance of photonic gradient computation compared to electronic implementations?

Key findings

• The photonic architecture achieves trillions of multiply-accumulate (MAC) operations per second, enabling ultra-high-speed neural network training.
• Energy consumption is less than one picojoule per MAC operation, significantly improving energy efficiency over electronic systems.
• The system performs in-situ gradient computation for each layer using photonic matrix-vector multiplication, reducing latency and hardware overhead.
• Experimental results demonstrate successful training of a deep neural network on the MNIST dataset using only on-chip photonic MAC operations.
• The direct feedback alignment algorithm enables stable and efficient training without requiring backpropagation through the network.
• The CMOS-compatible design supports integration with existing electronic systems, enabling hybrid photonic-electronic AI accelerators.