[Paper Review] PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory

Orian Leitersdorf, Ronny Ronen+1 more|arXiv (Cornell University)|Jun 9, 2022

Advanced Memory and Neural Computing4 citations

TL;DR

This paper proposes practical, efficient designs for memristive partitions in Processing-in-Memory (PIM) architectures to overcome the latency-throughput trade-off in stateful logic computation. By introducing half-gates for low peripheral overhead and minimizing control messages via shared indices and pattern generators, the authors achieve up to 11× speedup in 32-bit multiplication with only 1.2× control overhead compared to an idealized model, enabling scalable, high-performance in-memory computing.

ABSTRACT

Digital memristive processing-in-memory overcomes the memory wall through a fundamental storage device capable of stateful logic within crossbar arrays. Dynamically dividing the crossbar arrays by adding memristive partitions further increases parallelism, thereby overcoming an inherent trade-off in memristive processing-in-memory. The algorithmic topology of partitions is highly unique, and was recently exploited to accelerate multiplication (11x with 32 partitions) and sorting (14x with 16 partitions). Yet, the physical implementation of memristive partitions, such as the peripheral decoders and the control message, has never been considered and may lead to vast impracticality. This paper overcomes that challenge with several novel techniques, presenting efficient practical designs of memristive partitions. We begin by formalizing the algorithmic properties of memristive partitions into serial, parallel, and semi-parallel operations. Peripheral overhead is addressed via a novel technique of half-gates that enables efficient decoding with negligible overhead. Control overhead is addressed by carefully reducing the operation set of memristive partitions, while resulting in negligible performance impact, by utilizing techniques such as shared indices and pattern generators. Ultimately, these efficient practical solutions, combined with the vast algorithmic potential, may revolutionize digital memristive processing-in-memory.

Motivation & Objective

• Address the impracticality of implementing memristive partitions due to high peripheral and control overhead in prior algorithmic-only works.
• Overcome the inherent latency-throughput trade-off in memristive PIM by enabling parallel stateful logic operations across dynamically partitioned crossbar arrays.
• Design physically realizable partition architectures that maintain high algorithmic performance while minimizing area, energy, and control complexity.
• Demonstrate that practical partitioning is feasible and scalable by reducing control message size and peripheral logic without sacrificing performance.
• Enable widespread adoption of memristive PIM for large-scale applications by making partition-based acceleration both efficient and implementable.

Proposed method

• Introduce a novel half-gate technique to reduce peripheral decoder complexity, achieving lower area and power than baseline crossbars.
• Formalize partition operations into serial, parallel, and semi-parallel topologies to guide efficient implementation.
• Minimize control overhead by restricting the operation set to essential logic types (e.g., NOT, NOR), reducing message length by 85% compared to unrestricted models.
• Employ shared indices and pattern generators to encode control signals efficiently, reducing the number of unique control bits needed.
• Design three partition models—unlimited, standard, and minimal—offering trade-offs between flexibility and implementation efficiency.
• Evaluate designs using a 32-bit multiplication case study, comparing latency, control overhead, area, and energy across models.

Experimental results

Research questions

• RQ1 Can memristive partitions be practically implemented without incurring prohibitive peripheral or control overhead?
• RQ2 How can control message size be minimized in partitioned PIM without significantly degrading performance?
• RQ3 What is the impact of peripheral complexity on area and energy efficiency in partitioned memristive crossbars?
• RQ4 To what extent can algorithmic performance gains be preserved when restricting the operation set in partitioned PIM?
• RQ5 How do different partitioning models (unlimited, standard, minimal) compare in terms of latency, control overhead, and area efficiency?

Key findings

• The half-gate technique reduces peripheral decoder complexity, resulting in lower area overhead than a baseline crossbar without partitions.
• The minimal partition model reduces control message length to 36 bits (vs. 607 bits in the unlimited model), achieving only 1.2× overhead compared to the baseline.
• The minimal model incurs only 1.32× latency increase compared to the idealized unlimited model, while still achieving 8.6× speedup over a serial multiplier.
• Control overhead is the primary bottleneck in practical partitioning; the proposed techniques reduce it by 20× compared to unrestricted models.
• The algorithmic area overhead is higher than serial execution due to intermediate memristors, but this is outweighed by performance gains and is manageable with efficient encoding.
• Energy consumption increases by 2.1× due to higher gate count from parallelism, but this is justified by the 8.6× latency reduction in multiplication.