[Paper Review] PIMBALL: Binary Neural Networks in Spintronic Memory

Salonik Resch, S. Karen Khatamifard+6 more|arXiv (Cornell University)|Dec 10, 2018

Advanced Memory and Neural Computing48 references4 citations

TL;DR

PIMBALL proposes a spintronic, in-memory computing architecture that accelerates binary neural networks (BNNs) using spin-transfer torque magnetic random-access memory (STT-MRAM) arrays, performing all BNN operations—including XNOR, pop-count, and thresholding—entirely within the memory array without external digital logic. It achieves significantly higher energy efficiency than CPU, GPU, and FPGA-based implementations while enabling high throughput through massive array-level parallelism.

ABSTRACT

Neural networks span a wide range of applications of industrial and commercial significance. Binary neural networks (BNN) are particularly effective in trading accuracy for performance, energy efficiency or hardware/software complexity. Here, we introduce a spintronic, re-configurable in-memory BNN accelerator, PIMBALL: Processing In Memory BNN AcceL(L)erator, which allows for massively parallel and energy efficient computation. PIMBALL is capable of being used as a standard spintronic memory (STT-MRAM) array and a computational substrate simultaneously. We evaluate PIMBALL using multiple image classifiers and a genomics kernel. Our simulation results show that PIMBALL is more energy efficient than alternative CPU, GPU, and FPGA based implementations while delivering higher throughput.

Motivation & Objective

• Address the energy and performance bottlenecks of traditional neural network accelerators by leveraging in-memory computing in spintronic memory.
• Overcome the limitations of conventional accelerators that require frequent off-chip memory access due to limited on-chip storage for BNN parameters.
• Design a reconfigurable, scalable, and energy-efficient PIM substrate tailored for BNNs using STT-MRAM with native support for bitwise and accumulation operations.
• Eliminate the need for external digital or analog logic circuits by performing all BNN computation directly within the memory array.
• Demonstrate that a PIM-based architecture can achieve superior energy efficiency and competitive throughput for BNN inference at scale.

Proposed method

• Utilizes a modified STT-MRAM array architecture—PIMBALL—where each memory cell supports in-memory computation via spintronic logic operations such as XNOR and pop-count.
• Employs a reconfigurable memory array design that allows any row to be dynamically assigned to any computational task, enabling algorithmic flexibility.
• Performs all core BNN operations (XNOR, pop-count, batch normalization, thresholding) directly within the memory array using spintronic physics and array-level parallelism.
• Leverages the inherent non-volatility and bit-serial nature of STT-MRAM to support low-power, persistent storage and computation in a single substrate.
• Integrates pipelining and array-level parallelism to achieve high throughput despite potentially slower individual cycle times compared to FPGA accelerators.
• Avoids external sense amplifiers or auxiliary processing units by embedding all computational logic within the memory array structure, enabling full in-memory processing.

Experimental results

Research questions

• RQ1 Can a spintronic memory array be reconfigured to perform all essential operations of a binary neural network (e.g., XNOR, pop-count, thresholding) without external digital logic?
• RQ2 How does the energy efficiency of a PIM-based BNN accelerator compare to conventional CPU, GPU, and FPGA implementations?
• RQ3 To what extent can array-level parallelism in PIMBALL compensate for potentially slower individual operation cycles to achieve high throughput?
• RQ4 Can the proposed PIMBALL architecture maintain high accuracy while achieving extreme energy efficiency in BNN inference?
• RQ5 Is it feasible to scale the PIMBALL architecture to larger networks such as those used in CIFAR-10 and ImageNet without sacrificing performance or efficiency?

Key findings

• PIMBALL achieves significantly higher energy efficiency than CPU, GPU, and FPGA-based BNN accelerators, with power consumption reduced to a fraction of that of FPGA counterparts.
• Through massive array-level parallelism and pipelining, PIMBALL can outperform FPGA-based implementations in throughput while maintaining superior energy efficiency.
• All core BNN operations—including XNOR, pop-count, batch normalization, and thresholding—are performed entirely within the memory array, eliminating the need for external digital or analog circuitry.
• The PIMBALL architecture is fully reconfigurable: any row in the array can be dynamically assigned to different computational tasks based on algorithmic requirements.
• The design is scalable and suitable for larger networks such as those used in CIFAR-10 and SVHN, with simulation results confirming high performance and low energy consumption.
• The architecture maintains compatibility with standard STT-MRAM functionality when not used for computation, enabling dual use as both memory and accelerator.