[Paper Review] pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation.

João Dinis Ferreira, Gabriel Falcão+9 more|arXiv (Cornell University)|Apr 15, 2021

Parallel Computing and Optimization Techniques56 references22 citations

TL;DR

pLUTo is a novel in-DRAM architecture that embeds massively parallel lookup tables (LUTs) within DRAM subarrays to enable efficient, energy-saving execution of complex operations directly in memory. By leveraging DRAM's high area density for LUT storage and computation, pLUTo achieves 33× speedup and 110× energy savings over CPU, and 8× speedup and 80× energy savings over GPU for a state-of-the-art binary neural network.

ABSTRACT

Data movement between main memory and the processor is a significant contributor to the execution time and energy consumption of memory-intensive applications. This data movement bottleneck can be alleviated using Processing-in-Memory (PiM), which enables computation inside the memory chip. However, existing PiM architectures often lack support for complex operations, since supporting these operations increases design complexity, chip area, and power consumption. We introduce pLUTo (processing-in-memory with lookup table [LUT] operations), a new DRAM substrate that leverages the high area density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs). The use of LUTs enables the efficient execution of complex operations in-memory, which has been a long-standing challenge in the domain of PiM. When running a state-of-the-art binary neural network in a single DRAM subarray, pLUTo outperforms the baseline CPU and GPU implementations by $33 imes$ and $8 imes$, respectively, while simultaneously achieving energy savings of $110 imes$ and $80 imes$.

Motivation & Objective

• To address the data movement bottleneck in memory-intensive workloads by enabling computation directly within DRAM.
• To overcome the limitations of existing Processing-in-Memory (PiM) architectures that lack support for complex operations due to design complexity and area overhead.
• To enable efficient execution of complex operations in memory using high-density, massively parallel lookup tables (LUTs) within DRAM.
• To achieve significant performance and energy efficiency improvements for general-purpose, memory-intensive workloads like binary neural networks.

Proposed method

• pLUTo integrates LUTs directly into DRAM subarrays using the existing memory cell structure, exploiting DRAM's high area density for massive parallelism.
• It enables parallel querying of LUTs across all memory cells in a subarray, allowing simultaneous execution of complex operations through content-addressable lookup.
• The architecture supports arbitrary function computation by encoding functions as LUTs stored in DRAM, eliminating the need for complex logic units.
• It leverages existing DRAM read/write paths and timing to minimize area and power overhead while maintaining compatibility with standard DRAM operation.
• The design enables in-memory execution of complex operations such as nonlinear activation functions in neural networks by mapping them to pre-stored LUTs.
• The system is evaluated using a binary neural network workload, demonstrating high throughput and low latency via LUT-based computation in a single DRAM subarray.

Experimental results

Research questions

• RQ1 Can LUTs be efficiently embedded in DRAM to enable massively parallel in-memory computation of complex operations?
• RQ2 How does the integration of LUTs in DRAM affect area, power, and performance compared to traditional CPU and GPU execution?
• RQ3 To what extent can in-memory LUT-based computation reduce data movement and improve energy efficiency for memory-intensive workloads?
• RQ4 Can pLUTo achieve high performance and energy savings for real-world workloads like binary neural networks compared to conventional accelerators?

Key findings

• pLUTo achieves a 33× speedup over a baseline CPU when executing a state-of-the-art binary neural network.
• It delivers 110× energy savings compared to the CPU for the same workload.
• pLUTo achieves an 8× speedup over a GPU while realizing 80× energy savings.
• The performance and energy gains are attributed to the elimination of data movement and the exploitation of massive parallelism via embedded LUTs in DRAM.
• The architecture demonstrates that complex operations can be efficiently executed in memory using LUTs without requiring dedicated logic units.
• The results show that DRAM’s high area density can be effectively leveraged to store and query LUTs at scale, enabling practical in-memory computation.