[Paper Review] Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems

Lavanya Subramanian, Vivek Seshadri+3 more|arXiv (Cornell University)|May 15, 2018

Parallel Computing and Optimization Techniques52 references3 citations

TL;DR

This paper proposes MISE, a lightweight model that accurately estimates application slowdowns in shared main memory systems by using request service rate as a proxy for performance. By periodically prioritizing each application to estimate its 'alone' performance, MISE enables predictable quality-of-service and fairness through improved memory scheduling, outperforming prior techniques in both slowdown estimation accuracy and system fairness.

ABSTRACT

This paper summarizes the ideas and key concepts in MISE (Memory Interference-induced Slowdown Estimation), which was published in HPCA 2013 [97], and examines the work's significance and future potential. Applications running concurrently on a multicore system interfere with each other at the main memory. This interference can slow down different applications differently. Accurately estimating the slowdown of each application in such a system can enable mechanisms that can enforce quality-of-service. While much prior work has focused on mitigating the performance degradation due to inter-application interference, there is little work on accurately estimating slowdown of individual applications in a multi-programmed environment. Our goal is to accurately estimate application slowdowns, towards providing predictable performance. To this end, we first build a simple Memory Interference-induced Slowdown Estimation (MISE) model, which accurately estimates slowdowns caused by memory interference. We then leverage our MISE model to develop two new memory scheduling schemes: 1) one that provides soft quality-of-service guarantees, and 2) another that explicitly attempts to minimize maximum slowdown (i.e., unfairness) in the system. Evaluations show that our techniques perform significantly better than state-of-the-art memory scheduling approaches to address the same problems. Our proposed model and techniques have enabled significant research in the development of accurate performance models [35, 59, 98, 110] and interference management mechanisms [66, 99, 100, 108, 119, 120].

Motivation & Objective

• Address unpredictable performance degradation in multicore systems due to memory interference between concurrent applications.
• Overcome the lack of accurate online slowdown estimation for individual applications in multi-programmed environments.
• Enable predictable performance and fairness by accurately estimating application slowdowns under shared memory contention.
• Develop practical memory scheduling mechanisms that leverage accurate slowdown estimation for quality-of-service and fairness guarantees.
• Provide a simple, hardware-efficient model that can be integrated into existing memory controllers with minimal changes.

Proposed method

• Model application slowdown as the ratio of its estimated 'alone' request service rate to its actual 'shared' request service rate.
• Use the memory controller to track the shared request service rate (SRSR) of each application in real time.
• Estimate the alone request service rate (ARSR) by periodically giving each application the highest priority to minimize interference during measurement.
• Leverage the MISE model to design two memory scheduling schemes: one for soft quality-of-service and another to minimize maximum slowdown (unfairness).
• Apply the MISE model to real hardware using SPEC CPU2006 benchmarks and microbenchmarks to validate performance estimation accuracy.
• Use a memory bandwidth partitioning scheme that prioritizes one application at a time, simplifying scheduler logic compared to ranking-based approaches.

Experimental results

Research questions

• RQ1 How accurately can application slowdown be estimated in a shared main memory system with concurrent workloads?
• RQ2 Can request service rate serve as a reliable proxy for application performance in memory-bound workloads?
• RQ3 How does prioritizing an application for brief intervals improve the accuracy of alone-performance estimation compared to interference-aware estimation?
• RQ4 Can accurate slowdown estimation enable effective memory scheduling for quality-of-service and fairness guarantees?
• RQ5 To what extent can the MISE model be applied to different memory technologies beyond DRAM?

Key findings

• The performance of memory-bound applications is directly proportional to the rate at which their memory requests are served, validating request service rate as a performance proxy.
• Estimating alone-performance by prioritizing an application for short intervals yields significantly more accurate slowdown estimates than methods that estimate while interference is present.
• The proposed memory scheduling schemes based on MISE outperform state-of-the-art approaches in reducing maximum slowdown and improving fairness.
• The MISE model achieves high accuracy with minimal hardware changes, requiring only simple prioritization logic in the memory controller.
• The MISE model enables effective quality-of-service and fairness mechanisms without requiring complex comparator logic, making it more deployable than ranking-based scheduling schemes.
• The principles of MISE are generalizable to other shared resources such as caches, I/O, and networks, and are applicable to emerging memory technologies like phase-change memory and STT-MRAM.