[Paper Review] Preliminary Performance Estimations and Benchmark Results for a Software-based Fault-Tolerance Approach aboard Miniaturized Satellite Computers

Christian Fuchs, Todor Stefanov+2 more|arXiv (Cornell University)|Jun 7, 2017

Software Reliability and Analysis Research1 references3 citations

TL;DR

This paper presents a software-based fault-tolerance approach for miniaturized satellite computers using a multi-stage architecture combining thread-level distributed self-validation, FPGA reconfiguration, and mixed criticality on modern multiprocessor SoCs. It achieves median performance degradation of 9% (best-case) and 26% (worst-case) in a Linux-based C implementation, demonstrating feasibility for high-performance, low-cost space missions without proprietary hardware.

ABSTRACT

Modern embedded technology is a driving factor in satellite miniaturization, contributing to a massive boom in satellite launches and a rapidly evolving new space industry. Miniaturized satellites however suffer from low reliability, as traditional hardware-based fault-tolerance (FT) concepts are ineffective for on-board computers (OBCs) utilizing modern systems-on-a-chip (SoC). Larger satellites therefore continue to rely on proven processors with large feature sizes. Software-based concepts have largely been ignored by the space industry as they were researched only in theory, and have not yet reached the level of maturity necessary for implementation. In related work, we presented the first integral, real-world solution to enable fault-tolerant general-purpose computing with modern multiprocessor-SoCs (MPSoCs) for spaceflight, thereby enabling their use in future high-priority space missions. The presented multi-stage approach consists of three FT stages, combining coarse-grained thread-level distributed self-validation, FPGA reconfiguration, and mixed criticality to assure long-term FT and excellent scalability for both resource constrained and critical high-priority space missions. As part of the ongoing implementation effort towards a hardware prototype, several software implementations were achieved and tested. This document contains an outline of the conducted tests, performance evaluation results, and supplementary information not included in the actual paper. It is being continuously expanded and updated.

Motivation & Objective

• To address the reliability gap in miniaturized satellites caused by the incompatibility of traditional hardware-based fault-tolerance with modern, radiation-sensitive SoCs.
• To develop a mature, practical software-based fault-tolerance solution for general-purpose computing in space, overcoming the industry's historical reluctance toward software-only approaches.
• To enable the use of commercial-off-the-shelf (COTS) MPSoCs in high-priority space missions by providing a scalable, fully software-controlled fault-tolerance framework.
• To validate the feasibility and performance characteristics of the approach through real-world benchmarking on a Linux-based prototype before hardware deployment.

Proposed method

• A three-stage fault-tolerance architecture combining coarse-grained thread-level distributed self-validation, FPGA reconfiguration, and mixed criticality for long-term reliability and scalability.
• Implementation of the first stage in user-space C using POSIX threading and system calls to simulate tile-based execution on a Linux system with 1kHz scheduling frequency.
• Benchmarking using a real scientific application derived from the James Webb Space Telescope’s MIRI instrument, processing 600 frames of 1-Megapixel data with varying post-processing runs.
• Use of a naive, unoptimized C implementation to enable pessimistic performance estimation and correctness validation prior to kernel-level or hardware deployment.
• Design and implementation of a demo MPSoC on a VCU118 FPGA using Xilinx MicroBlaze cores, AXI interconnects, and on-chip BRAM for program memory and validation memory.
• External supervision via GPIO pins and integration with ChipScope and MicroBlaze debug units to monitor consistency and agreement across tiles.

Experimental results

Research questions

• RQ1 Can a software-based fault-tolerance approach achieve acceptable performance degradation when implemented on modern COTS MPSoCs in a satellite context?
• RQ2 How does the performance of a software-based fault-tolerance stack vary across different workloads (compute-heavy vs. data-heavy) in a realistic embedded application?
• RQ3 To what extent can a prototype implementation on a Linux system with user-space threads provide reliable performance estimates for a future kernel-level or hardware-based deployment?
• RQ4 Can a fully software-controlled, non-proprietary fault-tolerance framework be implemented using standard FPGA tools and COTS components, avoiding reliance on custom radiation-hardened processors?

Key findings

• The naive C implementation on Linux showed a median best-case performance degradation of 9% and a worst-case degradation of 26% compared to an unprotected reference run.
• On average, the approach achieved 95% of the reference performance in best-case scenarios and 80% in worst-case scenarios across all test configurations.
• Data-heavy workloads exhibited better performance than compute-heavy ones, as the first stage's logic is dominated by function calls, integer operations, and comparisons.
• The performance degradation is expected to improve significantly in a kernel-level implementation, with drastically reduced thread-management overhead.
• Even with up to 50% performance degradation, the approach would still offer a factor-of-5 performance advantage over state-of-the-art radiation-hardened processors.
• The prototype MPSoC design on VCU118 successfully demonstrated the core architecture, including interconnects, validation memory, and GPIO-based supervision, with full resource utilization reported in the supplementary materials.