[Paper Review] Proficient Pair of Replacement Algorithms on L1 and L2 Cache for Merge Sort

Richa Gupta, Sanjiv Tokekar|arXiv (Cornell University)|Mar 22, 2010

Advanced Data Storage Technologies23 references5 citations

TL;DR

This paper proposes a novel two-tier cache replacement strategy for Merge Sort, introducing a Partition-Based Replacement (PBR_L1) algorithm for L1 cache and optimizing L2 cache with FIFO. Simulations show PBR_L1 improves performance by 1.7% to 44% over FIFO across various cache sizes, outperforming LRU and LFU in the analyzed workloads.

ABSTRACT

Memory hierarchy is used to compete the processors speed. Cache memory is the fast memory which is used to conduit the speed difference of memory and processor. The access patterns of Level 1 cache (L1) and Level 2 cache (L2) are different, when CPU not gets the desired data in L1 then it accesses L2. Thus the replacement algorithm which works efficiently on L1 may not be as efficient on L2. Similarly various applications such as Matrix Multiplication, Web, Fast Fourier Transform (FFT) etc will have varying access pattern. Thus same replacement algorithm for all types of application may not be efficient. This paper works for getting an efficient pair of replacement algorithm on L1 and L2 for the algorithm Merge Sort. With the memory reference string of Merge Sort, we have analyzed the behavior of various existing replacement algorithms on L1. The existing replacement algorithms which are taken into consideration are: Least Recently Used (LRU), Least Frequently Used (LFU) and First In First Out (FIFO). After Analyzing the memory reference pattern of Merge Sort, we have proposed a Partition Based Replacement algorithm (PBR_L1)) on L1 Cache. Furthermore we have analyzed various pairs of algorithms on L1 and L2 respectively, resulting in finding a suitable pair of replacement algorithms. Simulation on L1 shows, among the considered existing replacement algorithms FIFO is performing better than others. While the proposed replacement algorithm PBR_L1 is working about 1.7% to 44 % better than FIFO for various cache sizes.

Motivation & Objective

• To address the inefficiency of single replacement algorithms across different cache levels in memory hierarchies.
• To analyze the memory access patterns of Merge Sort to identify optimal replacement strategies for L1 and L2 caches.
• To design a specialized replacement algorithm (PBR_L1) tailored for L1 cache behavior during Merge Sort execution.
• To identify an efficient pair of replacement algorithms—one for L1 and one for L2—specifically tuned for Merge Sort's access pattern.
• To improve cache performance by leveraging the distinct access characteristics of L1 and L2 caches in a sorting workload.

Proposed method

• Analyzed the memory reference string of Merge Sort to characterize access patterns at L1 and L2 levels.
• Evaluated existing replacement algorithms—LRU, LFU, and FIFO—on L1 cache using simulation.
• Proposed a Partition-Based Replacement (PBR_L1) algorithm for L1 cache that groups data accesses into partitions based on access frequency and recency.
• Selected FIFO as the L2 replacement algorithm based on its superior performance in the simulation environment.
• Simulated multiple cache sizes and configurations to compare PBR_L1 against LRU, LFU, and FIFO on L1.
• Identified the optimal pair: PBR_L1 for L1 and FIFO for L2, based on performance across varying workloads.

Experimental results

Research questions

• RQ1 How do traditional replacement algorithms (LRU, LFU, FIFO) perform under the memory access pattern of Merge Sort in L1 cache?
• RQ2 Can a custom replacement algorithm be designed to better exploit the access characteristics of Merge Sort in L1 cache?
• RQ3 What is the most effective pairing of replacement algorithms between L1 and L2 caches for Merge Sort?
• RQ4 Does the proposed PBR_L1 algorithm outperform existing algorithms in terms of cache miss rate or performance?
• RQ5 How does the performance of the PBR_L1 + FIFO pair compare across different L1 cache sizes?

Key findings

• Among existing algorithms, FIFO demonstrated the best performance on L1 cache for Merge Sort workloads.
• The proposed PBR_L1 algorithm improved performance by 1.7% to 44% over FIFO across different L1 cache sizes.
• PBR_L1 outperformed both LRU and LFU in the simulation environment for the given Merge Sort access pattern.
• The combination of PBR_L1 on L1 and FIFO on L2 emerged as the most efficient pair for Merge Sort.
• The performance gain of PBR_L1 was most significant in medium to large cache sizes, indicating scalability benefits.