[Paper Review] Q-EEGNet: an Energy-Efficient 8-bit Quantized Parallel EEGNet Implementation for Edge Motor-Imagery Brain--Machine Interfaces

Tibor Schneider, Xiaying Wang+3 more|arXiv (Cornell University)|Apr 24, 2020

EEG and Brain-Computer InterfacesNeuroscience22 references41 citations

TL;DR

This paper presents Q-EEGNet, an 8-bit quantized, energy-efficient implementation of EEGNet for motor-imagery brain-machine interfaces on edge devices. By combining quantization-aware training, hardware-aware parallelization on the Mr. Wolf RISC-V SoC, and an interleaved computation paradigm, the authors achieve 64× speedup and 85% memory reduction with only 0.4% accuracy loss, resulting in 5.82 ms inference time and 0.627 mJ energy consumption—256× more energy-efficient than prior ARM Cortex-M7 implementations.

ABSTRACT

Motor-Imagery Brain--Machine Interfaces (MI-BMIs)promise direct and accessible communication between human brains and machines by analyzing brain activities recorded with Electroencephalography (EEG). Latency, reliability, and privacy constraints make it unsuitable to offload the computation to the cloud. Practical use cases demand a wearable, battery-operated device with low average power consumption for long-term use. Recently, sophisticated algorithms, in particular deep learning models, have emerged for classifying EEG signals. While reaching outstanding accuracy, these models often exceed the limitations of edge devices due to their memory and computational requirements. In this paper, we demonstrate algorithmic and implementation optimizations for EEGNET, a compact Convolutional Neural Network (CNN) suitable for many BMI paradigms. We quantize weights and activations to 8-bit fixed-point with a negligible accuracy loss of 0.4% on 4-class MI, and present an energy-efficient hardware-aware implementation on the Mr.Wolf parallel ultra-low power (PULP) System-on-Chip (SoC) by utilizing its custom RISC-V ISA extensions and 8-core compute cluster. With our proposed optimization steps, we can obtain an overall speedup of 64x and a reduction of up to 85% in memory footprint with respect to a single-core layer-wise baseline implementation. Our implementation takes only 5.82 ms and consumes 0.627 mJ per inference. With 21.0GMAC/s/W, it is 256x more energy-efficient than an EEGNET implementation on an ARM Cortex-M7 (0.082GMAC/s/W).

Motivation & Objective

• Address the challenge of deploying accurate, low-latency EEG-based brain-machine interfaces (BMIs) on power-constrained, wearable edge devices.
• Overcome the limitations of traditional single-core, floating-point implementations that are too slow and power-hungry for real-time BMI applications.
• Achieve high inference efficiency on resource-limited microcontrollers by combining model quantization with hardware-aware optimization.
• Enable on-device, privacy-preserving BMI inference by eliminating cloud offloading and minimizing energy consumption.

Proposed method

• Quantize EEGNet weights and activations to 8-bit fixed-point using quantization-aware training and Random Partition Relaxation (RPR), preserving 99.6% of original accuracy.
• Implement the quantized model on the Mr. Wolf RISC-V SoC using custom ISA extensions and a 8-core compute cluster for parallel execution.
• Introduce an interleaved computation strategy that overlaps temporal and spatial convolutional layers, reducing memory footprint by up to 85%.
• Optimize memory access and computation through feature map replication, BN layer fusion, and loop unrolling using the PULP-DSP library.
• Utilize vectorized integer operations to replace floating-point arithmetic, enabling efficient execution on ultra-low-power MCUs.
• Apply compiler-level optimizations including instruction reordering and division reduction to further improve performance and energy efficiency.

Experimental results

Research questions

• RQ1 Can 8-bit quantization of EEGNet be applied to edge devices with negligible accuracy loss while maintaining real-time performance?
• RQ2 How can parallel execution on a multi-core RISC-V SoC improve inference speed and energy efficiency for EEG-based BMIs?
• RQ3 Can an interleaved computation model reduce memory footprint in CNN inference on memory-constrained embedded systems?
• RQ4 To what extent can hardware-aware optimizations, such as custom ISA usage and memory access reorganization, enhance energy efficiency in edge AI inference?
• RQ5 How does the energy efficiency of a custom-optimized Q-EEGNet implementation compare to general-purpose deep learning libraries on similar platforms?

Key findings

• Q-EEGNet achieves only 0.4% accuracy loss (70.9% on BCI Competition IV-2a) when quantized to 8-bit fixed-point, preserving high classification performance.
• The optimized implementation on Mr. Wolf runs inference in 5.82 ms at 350 MHz, consuming only 0.627 mJ per inference.
• The system achieves 64× speedup over a single-core baseline implementation through parallelization and algorithmic optimizations.
• Memory footprint is reduced by up to 85% (from 230.29 kB to 35.41 kB) using an interleaved layer computation strategy.
• Energy efficiency reaches 20.957 GMAC/s/W, making Q-EEGNet 256× more energy-efficient than a comparable EEGNet on ARM Cortex-M7.
• The implementation outperforms general-purpose libraries like PULP-NN and CUBE.AI by 3× in speed and 256× in energy efficiency, demonstrating the advantage of application-specific optimization.