[Paper Review] Simulation of the IEEE 1588 Precision Time Protocol in OMNeT++

Wolfgang Wallner|arXiv (Cornell University)|Sep 21, 2016

Network Time Synchronization Technologies2 references3 citations

TL;DR

This paper presents a modular, open-source simulation framework for IEEE 1588 Precision Time Protocol (PTP) in OMNeT++, enabling realistic modeling of oscillator noise and PTP synchronization. It implements a Powerlaw Noise model via LibPLN and a configurable PTP stack with BMC, delay measurement, and PI-based clock correction, offering a freely available, extensible tool for Design Space Exploration (DSE) of PTP networks with sub-microsecond precision.

ABSTRACT

Real-time systems rely on a distributed global time base. As any physical clock device suffers from noise, it is necessary to provide some kind of clock synchronization to establish such a global time base. Different clock synchronization methods have been invented for individual application domains. The Precision Time Protocol (PTP), which is specified in IEEE 1588, is another interesting option. It targets local networks, where it is acceptable to assume small amounts of hardware support, and promises sub-microsecond precision. PTP provides many different implementation and configuration options, and thus the Design Space Exploration (DSE) is challenging. In this paper we discuss the implementation of realistic clock noise and its synchronization via PTP in OMNeT++. The components presented in this paper are intended to assist engineers with the configuration of PTP networks.

Motivation & Objective

• To enable accurate simulation of clock synchronization in real-time systems using the IEEE 1588 Precision Time Protocol (PTP).
• To model realistic oscillator noise—particularly Powerlaw Noise—within a Discrete Event Simulation (DES) environment like OMNeT++.
• To support Design Space Exploration (DSE) of PTP networks by providing a modular, extensible simulation framework.
• To offer a freely available, open-source implementation of PTP components for research and educational use.

Proposed method

• Implementation of a generic clock model in OMNeT++ with extensible noise models, including Powerlaw Noise (PLN) via a custom library (LibPLN).
• Development of a PTP stack compliant with IEEE 1588-2008, supporting master-slave hierarchy via the Best Master Clock (BMC) algorithm.
• Integration of path delay estimation using two-step delay measurement and Sync/Follow-up message exchange.
• Design of a PI (proportional-integral) controller for clock servo correction to minimize offset between slave and master clocks.
• Modular architecture using OMNeT++ compound and simple modules for PTP nodes, ports, and state tracking.
• Support for logging, signal tracing, and statistics collection to enable detailed analysis of PTP behavior and algorithm execution.

Experimental results

Research questions

• RQ1 How can realistic oscillator noise, particularly Powerlaw Noise, be efficiently simulated in a Discrete Event Simulation (DES) environment like OMNeT++?
• RQ2 To what extent can a PTP simulation in OMNeT++ accurately model the synchronization behavior of real IEEE 1588-2008-compliant networks?
• RQ3 How effective is the proposed PI-based clock servo in minimizing clock offset under realistic noise conditions?
• RQ4 What is the feasibility and modularity of implementing a full-featured, open-source PTP simulation stack in OMNeT++?
• RQ5 How can the simulation framework support Design Space Exploration (DSE) of PTP configurations, including different profiles and network topologies?

Key findings

• The simulation framework successfully models Powerlaw Noise using LibPLN, enabling realistic oscillator behavior in OMNeT++ simulations.
• The PTP stack correctly implements the Best Master Clock (BMC) algorithm, enabling dynamic master-slave hierarchy formation.
• Path delay estimation via two-step method is accurately simulated, supporting sub-microsecond synchronization precision.
• The PI controller effectively reduces clock offset, demonstrating stable and accurate clock correction in the presence of noise.
• The entire framework is released as open source under GPL and BSD licenses, with components available on GitHub for community use and extension.
• The simulation supports detailed logging and signal tracing, enabling full visibility into BMC execution, state transitions, and algorithm decisions.