[Paper Review] Stream Processor Generator for HPC to Embedded Applications on FPGA-based System Platform

Kentaro Sano, H. Suzuki+3 more|arXiv (Cornell University)|Aug 21, 2014

Parallel Computing and Optimization Techniques8 references8 citations

TL;DR

This paper presents SPGen, a stream processor generator for FPGA-based system-on-chip platforms that automates the design of high-throughput, pipelined stream processors using a domain-specific high-level description language. By generating HDL code from this description, SPGen enables rapid exploration of design space and achieves performance comparable to or better than hand-optimized implementations, as validated through fluid dynamics computation workloads.

ABSTRACT

This paper presents a stream processor generator, called SPGen, for FPGA-based system-on-chip platforms. In our research project, we use an FPGA as a common platform for applications ranging from HPC to embedded/robotics computing. Pipelining in application-specific stream processors brings FPGAs power-efficient and high-performance computing. However, poor productivity in developing custom pipelines prevents the reconfigurable platform from being widely and easily used. SPGen aims at assisting developers to design and implement high-throughput stream processors by generating their HDL codes with our domain-specific high-level stream processing description, called SPD.With an example of fluid dynamics computation, we validate SPD for describing a real application and verify SPGen for synthesis with a pipelined data-flow graph. We also demonstrate that SPGen allows us to easily explore a design space for finding better implementation than a hand-designed one.

Motivation & Objective

• To address the low productivity in designing custom pipelined stream processors for FPGAs across HPC and embedded applications.
• To enable efficient, high-performance computing on reconfigurable FPGA platforms through automated HDL code generation.
• To support rapid design space exploration for optimizing throughput and resource usage.
• To validate the effectiveness of the stream processing description (SPD) language on real-world HPC workloads.
• To demonstrate that automatically generated designs can outperform hand-optimized implementations.

Proposed method

• The authors introduce a domain-specific high-level stream processing description (SPD) language to specify dataflow and pipelining behavior.
• SPGen takes SPD specifications and automatically generates synthesizable HDL code for FPGA implementation.
• The tool supports pipelined data-flow graphs to maximize throughput and exploit parallelism.
• The method is validated using a fluid dynamics computation example to demonstrate real-world applicability.
• Design space exploration is enabled by parameterizing the SPD description and evaluating different configurations via SPGen.
• The generated designs are synthesized and verified on FPGA platforms to ensure functional correctness and performance.

Experimental results

Research questions

• RQ1 Can a high-level stream processing description language effectively express complex HPC workloads like fluid dynamics on FPGAs?
• RQ2 To what extent can SPGen automate the generation of high-throughput, pipelined stream processors for diverse application domains?
• RQ3 Can the automatically generated designs achieve performance comparable to or better than hand-optimized implementations?
• RQ4 How effective is SPGen in enabling rapid design space exploration for optimizing throughput and resource utilization?
• RQ5 What is the overhead or trade-off in using automated generation versus hand-coding for FPGA stream processors?

Key findings

• SPGen successfully generated HDL code from a fluid dynamics computation example, demonstrating the feasibility of expressing real HPC workloads using the SPD language.
• The generated designs achieved high throughput through effective pipelining of data-flow graphs on FPGA platforms.
• Design space exploration using SPGen revealed configurations that outperformed a hand-designed baseline implementation.
• The use of a high-level description language significantly reduced development effort while maintaining high performance.
• The toolchain enabled functional verification and synthesis of complex stream processors with minimal manual intervention.
• The results confirm that automated generation can produce competitive or superior designs compared to hand-coding, especially in early-stage exploration.