[Paper Review] The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm

Kunal Korgaonkar, Ronny Ronen+2 more|arXiv (Cornell University)|Oct 22, 2019

Advanced Memory and Neural Computing6 references4 citations

TL;DR

The Bitlet model is a parameterized analytical framework that evaluates the performance and efficiency of processing-in-memory (PIM) workloads by modeling throughput, operation complexity, data alignment, and energy consumption. It defines a litmus test to determine when PIM outperforms traditional CPU computing, revealing that PIM excels for operations with low operation complexity (OC) and high data-level parallelism, especially under power constraints.

ABSTRACT

This paper describes an analytical modeling tool called Bitlet that can be used, in a parameterized fashion, to understand the affinity of workloads to processing-in-memory (PIM) as opposed to traditional computing. The tool uncovers interesting trade-offs between operation complexity (cycles required to perform an operation through PIM) and other key parameters, such as system memory bandwidth, data transfer size, the extent of data alignment, and effective memory capacity involved in PIM computations. Despite its simplicity, the model has already proven useful. In the future, we intend to extend and refine Bitlet to further increase its utility.

Motivation & Objective

• To address the lack of a standardized analytical tool for evaluating the performance and efficiency of processing-in-memory (PIM) workloads.
• To define a litmus test that determines whether a given workload is better suited for PIM or traditional CPU/GPU architectures.
• To quantify the trade-offs between operation complexity, data alignment, memory bandwidth, and energy efficiency in PIM systems.
• To provide a parameterized model that enables sensitivity analysis of PIM performance across key architectural and technological parameters.

Proposed method

• Models PIM throughput using a row-wise, bit-serial processing model based on NOR operations within memristive memory arrays.
• Introduces a parameterized throughput equation (Eq. 1) that accounts for operation complexity (OC), number of memory arrays (MAT), row count (ROW), and cycle time (CT).
• Incorporates placement and alignment cost (PAC) as a performance penalty factor, modeling horizontal and vertical data moves required due to misalignment.
• Defines a CPU throughput model based on memory bandwidth (BW), data-parallelism (DIO), and operation complexity (OC), enabling direct comparison.
• Uses energy efficiency metrics (E^PIM and E^CPU) to compare PIM and CPU energy consumption per operation, especially for basic logic operations.
• Applies power constraints to limit the number of active memory arrays (MATs), modeling real-world system-level energy budgets.

Experimental results

Research questions

• RQ1 Under what conditions does PIM outperform traditional CPU architectures in terms of throughput and energy efficiency?
• RQ2 How do operation complexity (OC), data alignment (PAC), and memory bandwidth (BW) influence the performance trade-offs between PIM and CPU?
• RQ3 What is the crossover point where PIM becomes less efficient than CPU, and how does it vary with system parameters like MAT and DIO?
• RQ4 How does non-zero placement and alignment cost (PAC) affect PIM’s effective throughput and energy efficiency?
• RQ5 To what extent does energy efficiency favor PIM for low-complexity operations, and how does this advantage diminish as OC increases?

Key findings

• PIM outperforms CPU for operations with low operation complexity (OC), such as 16-bit addition (OC = 144), especially when data alignment is optimal (PAC = 0).
• For 16-bit addition with PAC = 1040, PIM throughput drops to 88 GOPS (12% of original 728 GOPS), demonstrating significant performance loss due to alignment overhead.
• The crossover point where CPU surpasses PIM shifts from OC ≈ 2500 to OC ≈ 5000 when data input/output size (DIO) increases from 24 to 48 bits, indicating a strong dependency on data size.
• Under a 20W power limit, PIM can support up to 1950 memory arrays (MATs), and throughput plateaus beyond this due to energy constraints.
• For a single-bit NOR operation (OC = 1), PIM consumes 0.1pJ compared to 45pJ for CPU (3× E^CPU), giving PIM a 450× energy efficiency advantage.
• When OC exceeds 7200, PIM’s energy efficiency advantage diminishes, and CPU becomes more efficient, indicating a hard limit on PIM’s suitability for high-complexity operations.