[Paper Review] The Brain on Low Power Architectures - Efficient Simulation of Cortical Slow Waves and Asynchronous States

Roberto Ammendola, A. Biagioni+11 more|arXiv (Cornell University)|Apr 10, 2018

Advanced Memory and Neural Computing3 citations

TL;DR

This paper evaluates the energy efficiency of simulating cortical slow waves using the DPSNN spiking neural network simulator on ARM-based low-power architectures versus traditional x86 servers. It demonstrates that ARM platforms achieve 3× lower energy-to-solution per synaptic event despite lower raw performance, highlighting their potential for energy-efficient brain simulation and future HPC systems.

ABSTRACT

Efficient brain simulation is a scientific grand challenge, a parallel/distributed coding challenge and a source of requirements and suggestions for future computing architectures. Indeed, the human brain includes about 10^15 synapses and 10^11 neurons activated at a mean rate of several Hz. Full brain simulation poses Exascale challenges even if simulated at the highest abstraction level. The WaveScalES experiment in the Human Brain Project (HBP) has the goal of matching experimental measures and simulations of slow waves during deep-sleep and anesthesia and the transition to other brain states. The focus is the development of dedicated large-scale parallel/distributed simulation technologies. The ExaNeSt project designs an ARM-based, low-power HPC architecture scalable to million of cores, developing a dedicated scalable interconnect system, and SWA/AW simulations are included among the driving benchmarks. At the joint between both projects is the INFN proprietary Distributed and Plastic Spiking Neural Networks (DPSNN) simulation engine. DPSNN can be configured to stress either the networking or the computation features available on the execution platforms. The simulation stresses the networking component when the neural net - composed by a relatively low number of neurons, each one projecting thousands of synapses - is distributed over a large number of hardware cores. When growing the number of neurons per core, the computation starts to be the dominating component for short range connections. This paper reports about preliminary performance results obtained on an ARM-based HPC prototype developed in the framework of the ExaNeSt project. Furthermore, a comparison is given of instantaneous power, total energy consumption, execution time and energetic cost per synaptic event of SWA/AW DPSNN simulations when executed on either ARM- or Intel-based server platforms.

Motivation & Objective

• To evaluate the energy efficiency of ARM-based HPC architectures for large-scale brain simulations.
• To benchmark the DPSNN simulator on low-power ARM platforms against traditional x86 server systems.
• To assess the performance and energy consumption of cortical slow wave simulations under varying network and computation loads.
• To identify architectural requirements for future interconnects and HPC systems optimized for neuroscience workloads.
• To validate ARM-based platforms as viable alternatives for energy-efficient scientific computing in computational neuroscience.

Proposed method

• The DPSNN simulator was ported to ARM-based platforms, including a second-generation NVIDIA Jetson TX1 SoC with ARMv8 architecture.
• Simulations of 10,000 LIFCA neurons with 18 million synapses were executed using 4 MPI processes on both ARM and x86 platforms.
• Time-to-solution, instantaneous power, total energy consumption, and energy cost per synaptic event were measured and compared.
• Network traffic characterization was performed to inform the design of low-latency, high-throughput interconnects for future HPC systems.
• The study used a controlled setup with identical neural network configurations across platforms to ensure fair comparison.
• Base-line power consumption was not subtracted, resulting in a pessimistic but realistic estimate of system-level energy use.

Experimental results

Research questions

• RQ1 How does the energy efficiency of ARM-based processors compare to x86 servers in simulating cortical slow waves using DPSNN?
• RQ2 What is the impact of network distribution on performance and energy consumption when simulating large-scale spiking neural networks?
• RQ3 How do different memory bandwidths and core counts affect the time-to-solution and energy-to-solution in DPSNN simulations?
• RQ4 Can low-power ARM platforms achieve competitive performance-per-watt for neuroscience simulation workloads?
• RQ5 What are the key bottlenecks in current off-the-shelf networking components when running DPSNN on distributed cores?

Key findings

• The ARM-based embedded platform consumed 528 J of energy to complete a 3-second simulation, while the x86 server platform consumed 2.3 kJ, resulting in a 4.4× reduction in total energy consumption on ARM.
• The x86 server platform completed the simulation in 9.1 seconds, while the ARM platform took 30 seconds, indicating a 3.3× longer time-to-solution on ARM.
• The instantaneous power consumption was 17.6 W on the ARM platform versus 253 W on the x86 server, a 14.4× reduction in real-time power draw.
• The energy cost per synaptic event was 2.2 μJ on the ARM platform and 9.8 μJ on the x86 platform, showing a 3× improvement in energy efficiency on ARM.
• Despite being 5× slower in raw computation speed, the x86 platform consumed approximately 3× more energy per unit of work, underscoring ARM’s superior energy efficiency.
• Excluding base-line power would further improve the energy-to-solution ratio by a factor of 4 on x86 and 2 on ARM, reinforcing the advantage of ARM in low-power scenarios.