[论文解读] Transformations of High-Level Synthesis Codes for High-Performance Computing

Johannes de Fine Licht, Maciej Besta+2 more|arXiv (Cornell University)|May 21, 2018

Parallel Computing and Optimization Techniques被引用 9

一句话总结

本文针对FPGA等空间架构上的高性能计算（HPC）场景，提出了一套全面的高层次综合（HLS）代码优化转换方法。该工作对流水线、内存和可扩展性转换进行了分类，通过系统化的代码优化和开源参考内核，实现了相较于原始HLS实现最高达29,950×的性能提升。

ABSTRACT

Spatial computing architectures promise a major stride in performance and energy efficiency over the traditional load/store devices currently employed in large scale computing systems. The adoption of high-level synthesis (HLS) from languages such as C++ and OpenCL has greatly increased programmer productivity when designing for such platforms. While this has enabled a wider audience to target spatial computing architectures, the optimization principles known from traditional software design are no longer sufficient to implement high-performance codes, due to fundamentally distinct aspects of hardware design, such as programming for deep pipelines, distributed memory resources, and scalable routing. To alleviate this, we present a collection of optimizing transformations for HLS, targeting scalable and efficient architectures for high-performance computing (HPC) applications. We systematically identify classes of transformations (pipelining, scalability, and memory), the characteristics of their effect on the HLS code and the resulting hardware (e.g., increasing data reuse or resource consumption), and the objectives that each transformation can target (e.g., resolve interface contention, or increase parallelism). We show how these can be used to efficiently exploit pipelining, on-chip distributed fast memory, and on-chip dataflow, allowing for massively parallel architectures. To quantify the effect of various transformations, we cover the optimization process of a sample set of HPC kernels, provided as open source reference codes. We aim to establish a common toolbox to guide both performance engineers and compiler engineers in tapping into the performance potential offered by spatial computing architectures using HLS.

研究动机与目标

• 通过识别硬件感知优化，弥合原始HLS代码与高性能空间架构之间的性能差距。
• 系统性地对HPC工作负载适用的HLS转换进行分类，重点关注流水线、内存层次结构和可扩展性。
• 提供一个实用且可复用的转换工具箱，指导性能工程师和编译器工程师优化HLS生成的硬件。
• 通过端到端优化HPC内核（包括stencil、矩阵乘法和N体问题）来验证这些转换的有效性。

提出的方法

• 基于对硬件资源使用和性能的影响，将关键HLS转换分类为三类：流水线、内存优化和可扩展性。
• 将传统CPU/GPU编译器优化映射到HLS场景，区分可直接应用、需适应调整以及因硬件差异而无关的优化。
• 应用如循环流水线、数组分区、数据重用增强和接口争用缓解等转换，以优化内核性能。
• 使用基于pragma的HLS工具流（Intel OpenCL和Xilinx Vivado HLS）在真实HPC内核上实现并评估转换效果。
• 将优化后的参考代码发布在GitHub上，作为性能工程的基准和教育资源。
• 通过与原始HLS实现相比的加速比指标，量化多种HPC内核上的性能提升。

实验结果

研究问题

• RQ1 在面向空间架构的高层次综合时，哪些传统编译器优化可直接应用，哪些需要适应调整？
• RQ2 如何系统性地将流水线、内存层次管理与数据流优化应用于HLS代码，以在FPGA上实现高性能？
• RQ3 对HPC内核应用一整套硬件感知转换后，其累积性能影响如何？
• RQ4 现有HLS编译器在多大程度上能自动应用这些优化？手动转换在实现峰值性能中扮演何种角色？
• RQ5 能否建立一个统一的转换工具箱，以指导性能工程师和编译器开发者优化HLS生成的硬件？

主要发现

• 应用硬件感知转换后，HPC内核的累积加速比最高达到29,950×，远超原始HLS实现。
• 传统软件优化（如循环不变量代码外移、循环规范化和循环倾斜）在HLS上下文中依然相关且有益。
• 流水线、内存分区和数据重用等转换显著提升了FPGA空间架构上的吞吐量并降低了延迟。
• 许多标准CPU/GPU编译器优化（如函数记忆化、标量替换）可直接应用于HLS，仅需极少调整。
• 由于综合时间过长且缺乏指令级并行性，大量传统编译器转换（如超编译、图划分、VLIW）在HLS中不可行或无关。
• 开源参考代码表明，HLS编译器无法自动实现性能提升，必须通过有意识的、有针对性的优化才能达成。