[Paper Review] Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm

Hadi Mardani Kamali|arXiv (Cornell University)|Jul 9, 2018

Advanced Data Compression Techniques16 references3 citations

TL;DR

This paper proposes MUCH-SWIFT, an FPGA-based HW/SW co-design architecture that accelerates K-means clustering using a two-level filtering algorithm built on binary kd-trees. By leveraging all processing cores in a ZYNQ Ultrascale+ SoC and optimizing data flow via a high-throughput DMA channel, the system achieves a 330× speedup over software-only implementations on large, high-dimensional datasets.

ABSTRACT

The capability of classifying and clustering a desired set of data is an essential part of building knowledge from data. However, as the size and dimensionality of input data increases, the run-time for such clustering algorithms is expected to grow superlinearly, making it a big challenge when dealing with BigData. K-mean clustering is an essential tool for many big data applications including data mining, predictive analysis, forecasting studies, and machine learning. However, due to large size (volume) of Big-Data, and large dimensionality of its data points, even the application of a simple k-mean clustering may become extremely time and resource demanding. Specially when it is necessary to have a fast and modular dataset analysis flow. In this paper, we demonstrate that using a two-level filtering algorithm based on binary kd-tree structure is able to decrease the time of convergence in K-means algorithm for large datasets. The two-level filtering algorithm based on binary kd-tree structure evolves the SW to naturally divide the classification into smaller data sets, based on the number of available cores and size of logic available in a target FPGA. The empirical result on this two-level structure over multi-core FPGA-based architecture provides 330X speed-up compared to a conventional software-only solution.

Motivation & Objective

• Address the growing computational challenge of accelerating K-means clustering on Big Data with high dimensionality and large volume.
• Overcome the limitations of pure software implementations, which suffer from superlinear runtime growth as data size increases.
• Leverage FPGA-based hardware acceleration to achieve high throughput and low latency in clustering workloads.
• Design a reconfigurable, scalable, and modular architecture that efficiently utilizes multi-core FPGA resources for dynamic clustering workloads.
• Integrate software optimization techniques (e.g., kd-tree filtering) with hardware parallelism to maximize performance and resource utilization.

Proposed method

• Implement a two-level filtering algorithm based on binary kd-trees to partition the search space and reduce redundant distance computations in K-means.
• Map the K-means algorithm to a ZYNQ Ultrascale+ SoC, utilizing both ARM processing cores and programmable logic for hybrid parallelism.
• Use a high-bandwidth, DMA-based PCIe interface to enable efficient data transfer between host memory and the ZYNQ SoC, minimizing I/O bottlenecks.
• Dynamically partition the clustering workload across available processing units based on the number of clusters and available FPGA resources.
• Optimize resource allocation by maximizing usage of BRAMs and DSPs to support up to 80 parallel arithmetic units for cluster computation.
• Apply software-level optimizations such as triangle inequality and fixed-point arithmetic to reduce computational overhead in hardware.

Experimental results

Research questions

• RQ1 Can a two-level filtering algorithm based on binary kd-trees significantly reduce the number of distance computations in K-means clustering on large datasets?
• RQ2 To what extent can HW/SW co-design on an FPGA platform like ZYNQ Ultrascale+ improve the performance of K-means clustering compared to pure software implementations?
• RQ3 How does the integration of multi-core ARM processors and programmable logic in a single SoC enable scalable and efficient parallelization of K-means?
• RQ4 What is the maximum feasible number of clusters that can be supported in a fully parallel FPGA-based K-means architecture before resource constraints limit performance?
• RQ5 How does the proposed architecture maintain high throughput and low latency when processing high-dimensional data with large input volumes?

Key findings

• The MUCH-SWIFT architecture achieves a 330× speedup over a conventional software-only K-means implementation on large datasets.
• The two-level kd-tree filtering algorithm reduces redundant distance calculations, significantly improving convergence time in high-dimensional data clustering.
• The system supports up to 20 clusters in a fully parallel configuration, enabling 80 parallel arithmetic units on the ZU9EG FPGA, maximizing hardware utilization.
• Resource utilization is optimized by prioritizing BRAM and DSP usage, which are critical for sustaining high-throughput parallel computation.
• The DMA-based PCIe interface enables efficient data movement between host and ZYNQ SoC, reducing I/O latency and supporting large input datasets.
• The architecture maintains high performance across varying cluster counts and data dimensions, with a 12× average speedup over prior work (Canilho et al., 2016), especially as cluster count increases.