[Paper Review] Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE

Kotaro Matsuoka, Ryotaro Banno+3 more|arXiv (Cornell University)|Oct 19, 2020

Cryptography and Data Security33 references4 citations

TL;DR

This paper presents Virtual Secure Platform (VSP), the first comprehensive, open-source, multi-opcode general-purpose processor over the TFHE fully homomorphic encryption scheme, enabling secure computation offloading. By integrating a five-stage pipelined processor, a custom ISA (CAHPv3), and optimized CMUX Memory structures, VSP achieves sub-second per-instruction latency—1,600× faster than the prior state-of-the-art FURISC, demonstrating practical feasibility for secure cloud-based execution of arbitrary C programs.

ABSTRACT

We present Virtual Secure Platform (VSP), the first comprehensive platform that implements a multi-opcode general-purpose sequential processor over Fully Homomorphic Encryption (FHE) for Secure Multi-Party Computation (SMPC). VSP protects both the data and functions on which the data are evaluated from the adversary in a secure computation offloading situation like cloud computing. We proposed a complete processor architecture with a five-stage pipeline, which improves the performance of the VSP by providing more parallelism in circuit evaluation. In addition, we also designed a custom Instruction Set Architecture (ISA) to reduce the gate count of our processor, along with an entire set of toolchains to ensure that arbitrary C programs can be compiled into our custom ISA. In order to speed up instruction evaluation over VSP, CMUX Memory based ROM and RAM constructions over FHE are also proposed. Our experiments show that both the pipelined architecture and the CMUX Memory technique are effective in improving the performance of the proposed processor. We provide an open-source implementation of VSP which achieves a per-instruction latency of less than 1 second. We demonstrate that compared to the best existing processor over FHE, our implementation runs nearly 1,600$ imes$ faster.

Motivation & Objective

• To address the lack of practical, general-purpose secure computation offloading platforms that protect both data and code from untrusted cloud servers.
• To overcome the performance bottleneck of existing FHE-based processors by introducing hardware-aware optimizations for TFHE.
• To enable compilation of arbitrary C programs into a secure, homomorphic execution environment via a custom ISA and full compiler toolchain.
• To demonstrate that secure computation offloading can be practical by achieving sub-second per-instruction latency on a real implementation.

Proposed method

• Designing a five-stage pipelined processor architecture over TFHE to increase parallelism and reduce instruction latency.
• Creating a custom Instruction Set Architecture (CAHPv3) to minimize gate count and improve efficiency in homomorphic evaluation.
• Developing CMUX Memory structures for ROM and RAM that leverage TFHE's leveled homomorphic encryption to accelerate memory access.
• Building a complete LLVM-based compiler toolchain to compile standard C programs into CAHPv3 machine code.
• Implementing and benchmarking the full stack on AWS p3.8xlarge instances to evaluate end-to-end performance.
• Using bootstrapping to manage noise growth and maintain correctness during long computations.

Experimental results

Research questions

• RQ1 Can a general-purpose, multi-opcode processor be efficiently implemented over FHE to enable secure computation offloading?
• RQ2 How can pipelining and memory optimization reduce latency in FHE-based processors?
• RQ3 To what extent can a custom ISA and compiler toolchain reduce gate count and improve performance in homomorphic execution?
• RQ4 Is it feasible to achieve practical performance for secure computation offloading using FHE, given current hardware constraints?

Key findings

• VSP achieves a per-instruction evaluation latency of 0.8 seconds, representing a 1,600× speedup over the prior state-of-the-art FURISC processor.
• The five-stage pipelined architecture significantly improves throughput by enabling concurrent evaluation of multiple instructions in the circuit.
• CMUX Memory structures reduce memory access latency by efficiently leveraging TFHE's leveled homomorphic encryption mode.
• The open-source VSP implementation supports full C language programs via an LLVM-based compiler stack and custom CAHPv3 ISA.
• Key generation, particularly the bootstrapping key, is the most time-consuming phase, taking ~55 seconds on AWS p3.8xlarge, but can be reused to reduce communication cost.
• Despite higher memory size (RAM ~1024× larger than ROM due to lack of vertical packing), the overall system remains practical for many workloads.