[Paper Review] VLSI Architecture of Compact Non-RLL Beacon-based Visible Light Communication Transmitter and Receiver

Duc-Phuc Nguyen, Dinh-Dung Le+3 more|arXiv (Cornell University)|May 9, 2018

Optical Wireless Communication Technologies20 references3 citations

TL;DR

This paper presents the first VLSI architecture for a compact, non-RLL beacon-based Visible Light Communication (VLC) transmitter and receiver that eliminates the need for run-length limited (RLL) coding through a pre-scrambler and Polar encoder, enabling flicker mitigation with improved code-rate (0.62) and reduced complexity. The receiver employs a 3-bit soft-decision filter to enable efficient soft-decoding of Polar codes, achieving superior bit-error-rate (BER) and frame-error-rate (FER) performance compared to RLL-based and Reed-Solomon-coded systems.

ABSTRACT

In this paper, we introduce a couple of hardware implementations of compact VLC transmitter and receiver for the first time. Compared with related works, our VLC transmitter is non-RLL one, that means flicker mitigation can be guaranteed even without RLL codes. In particular, we have utilized a centralized bit probability distribution of a prescrambler and a Polar encoder to create a non-RLL flicker mitigation solution. Moreover, at the receiver, a 3-bit soft-decision filter is proposed to analyze signals received from real VLC channel to extract log-likelihood ratio (LLR) values and feed them to the FEC decoder. Therefore, soft-decoding of Polar decoder can be implemented to improve the bit-error-rate (BER) performance of the VLC system. Finally, we introduce a novel very large scale integration (VLSI) architecture for the compact VLC transmitter and receiver; and synthesis our design under FPGA/ASIC synthesis tools. Due to the non-RLL basic, our system has an evidently good code-rate and a reduced-complexity compared with other RLL-based receiver works. Also, we present FPGA and ASIC synthesis results of the proposed architecture with evaluations of power consumption, area, energy-per-bits and so on.

Motivation & Objective

• To address the high computational complexity and hardware overhead of RLL-based VLC systems, especially in low-end MCUs and SoCs.
• To eliminate the need for RLL coding in VLC beacon systems by introducing a non-RLL flicker mitigation solution using pre-scrambling and Polar encoding.
• To design a compact, low-complexity VLSI architecture for both VLC transmitter and receiver that supports real-time soft-decoding for improved error correction.
• To evaluate the proposed system’s performance in terms of BER, FER, energy efficiency, area, and power consumption via FPGA and ASIC synthesis.
• To demonstrate that non-RLL systems can achieve better code-rate and error performance than traditional RLL or RS-coded systems.

Proposed method

• A pre-scrambler with a simple generating polynomial is used to centralize bit probability distribution within the range of 43.75%–63.75%, reducing run-length and ensuring DC balance without RLL constraints.
• A Polar encoder is applied after the pre-scrambler to generate non-RLL codewords with controlled run-length and improved spectral efficiency.
• A 3-bit soft-decision filter is designed at the receiver to extract log-likelihood ratio (LLR) values from real VLC channel signals, enabling soft-decoding of Polar codes.
• The system uses On-Off Keying (OOK) modulation with a low data rate to evaluate performance under realistic conditions.
• The VLSI architecture is synthesized using FPGA and ASIC tools, with performance metrics including area, power, throughput, and energy-per-bit evaluated.
• The design is compared with RLL-based and Reed-Solomon-coded systems using BER and FER curves under additive white Gaussian noise (AWGN) conditions.

Experimental results

Research questions

• RQ1 Can a non-RLL VLC system achieve flicker mitigation without relying on run-length limited (RLL) coding?
• RQ2 How does the combination of pre-scrambling and Polar encoding affect run-length and DC balance in short VLC beacon frames?
• RQ3 To what extent does soft-decision filtering improve BER and FER performance in a hardware-implemented VLC receiver?
• RQ4 What are the area, power, and energy efficiency trade-offs of the proposed non-RLL VLSI architecture compared to existing RLL-based designs?
• RQ5 Can a non-RLL system achieve better code-rate and error performance than traditional RLL or RS-coded systems?

Key findings

• The proposed non-RLL system achieves a code-rate of 0.62, significantly higher than RLL-based systems with code-rates of 0.49, 0.31, and 0.13.
• The pre-scrambler reduces the maximum run-length by up to 4.08 times when combined with a systematic Polar encoder (SPE), and by 1.9 times with a non-systematic encoder (NSPE).
• The BER performance of the non-RLL Polar-coded system outperforms RS-coded systems at equivalent or lower code-rates, particularly at code-rate 0.62.
• The FER performance of the proposed system surpasses that of related works, including RLL-based and RS-coded systems, under the same SNR conditions.
• The FPGA and ASIC synthesis results show favorable area and power efficiency, with energy-per-bit and hardware efficiency metrics quantified for system-level evaluation.
• The soft-decision filter enables effective LLR extraction from real VLC channels, making soft-decoding of Polar codes feasible in hardware.