[Paper Review] A 26 ps RMS time-to-digital converter core for Spartan-6 FPGAs

Sébastien Bourdeauducq|arXiv (Cornell University)|Mar 27, 2013

Advancements in PLL and VCO Technologies3 references16 citations

TL;DR

This paper presents a 26 ps RMS precision time-to-digital converter (TDC) core implemented in Spartan-6 FPGAs using carry chain-based delay lines with dual calibration: startup calibration for process variation and online calibration via ring oscillator frequency tracking to compensate for voltage and temperature drift. The design achieves sub-cycle resolution without dead time and is freely available under LGPL.

ABSTRACT

We have designed, implemented and tested a time-to-digital converter core in a low-cost Spartan-6 FPGA. Our design exploits the finite propagation speed in carry chains to realize a delay line in which the propagation distance of the incoming signal's edges is measured using hundreds of taps. This technique enables the core to reach a precision far better than the minimum switching period of the FPGA flip-flops. To compensate for process, voltage and temperature (PVT) effects, our design uses a combination of two techniques: startup calibration and online calibration. The startup calibration uses a statistical method to estimate the delay between the taps of the delay line and helps eliminate the effect of process variations. The online calibration, which takes place without disruption of the core's operation, uses a ring oscillator whose frequency instability is measured and used to compensate for subsequent voltage and temperature effects on the delay line. Our tests show that our design reaches a precision of 26 ps RMS over a temperature range of 37C to 48C.

Motivation & Objective

• To design a high-precision, low-cost TDC core for use in FPGA-based timing systems, particularly for particle physics applications.
• To overcome limitations of prior FPGA-based TDCs, including dead times during calibration and sensitivity to input signal statistics.
• To enable continuous, non-disruptive calibration that compensates for voltage and temperature variations in real time.
• To implement a fully open-source solution with freely available VHDL code under LGPL for reproducibility and integration.
• To achieve sub-picosecond resolution using only low-cost Spartan-6 FPGAs, avoiding expensive commercial TDC chips.

Proposed method

• The TDC uses a tapped delay line built from CARRY4 primitives in Spartan-6 FPGAs, with signal propagation measured via D flip-flop sampling at each tap.
• A startup calibration process uses a uniform-probability transition signal to build a histogram of raw timestamps, enabling LUT generation based on tap delay estimates.
• Online calibration employs a ring oscillator near the delay line; its frequency drift is measured and used to linearly interpolate and update the LUT in real time.
• Timestamps are computed as a combination of cycle count and fractional time from the calibrated LUT, with user-defined offset support.
• The system measures both rising and falling edge times, with polarity output distinguishing them.
• Differential measurements using two cables of different lengths are used to assess precision, isolating jitter from common-mode noise.

Experimental results

Research questions

• RQ1 Can a high-precision TDC be implemented in low-cost Spartan-6 FPGAs using only standard primitives and open-source design?
• RQ2 How can PVT-induced delay variations in FPGA carry chains be effectively compensated without introducing dead time?
• RQ3 Can online calibration based on ring oscillator frequency tracking achieve sub-30 ps RMS resolution over temperature and voltage variations?
• RQ4 Does the use of a non-uniform calibration signal (e.g., slightly offset clock) reduce startup calibration histogram variability?
• RQ5 Can the TDC maintain high throughput and low latency while supporting multiple channels on a single FPGA?

Key findings

• The TDC achieves 26 ps RMS jitter over a temperature range from 37°C to 48°C, demonstrating high precision under PVT variations.
• Differential measurements using 2ns and 4ns cables show a standard deviation of 37 ps, implying a per-channel jitter of 26 ps RMS when assuming independent Gaussian noise.
• Online calibration effectively tracks temperature and voltage drift, reducing LUT mismatch at higher temperatures compared to startup-only calibration.
• The online calibration system reduces the difference between LUTs calibrated at different temperatures to below the level of variation seen between two identical startup calibrations at the same temperature.
• The core exhibits low latency (6 system clock cycles) and high throughput, with only 3 cycles of dead time per event, which can be reduced to 1 cycle with minor architectural changes.
• The design supports multiple channels on a single FPGA (e.g., XC6SLX45T) with shared calibration logic, enabling scalable, cost-effective multi-channel timing systems.