[Paper Review] Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation

Marie Nguyen, Juanita Hoe|arXiv (Cornell University)|Oct 23, 2017

Embedded Systems Design Techniques8 references3 citations

TL;DR

This paper proposes amorphous dynamic partial reconfiguration (DPR), a technique that eliminates fixed partition boundaries in FPGA fabrics by allowing AFUs to be mapped to flexible, non-overlapping footprints at runtime. By compiling multiple footprint-optimized bitstream versions per AFU and dynamically selecting non-overlapping configurations, the method reduces resource fragmentation and improves placement success rates and reconfiguration efficiency compared to standard DPR with fixed partitions.

ABSTRACT

Dynamic partial reconfiguration (DPR) allows one region of an field-programmable gate array (FPGA) fabric to be reconfigured without affecting the operations on the rest of the fabric. To use an FPGA as a dynamically shared compute resource, one could partition and manage an FPGA fabric as multiple DPR partitions that can be independently reconfigured at runtime with different application function units (AFUs). Unfortunately, dividing a fabric into DPR partitions with fixed boundaries causes the available fabric resources to become fragmented. An AFU of a given size cannot be loaded unless a sufficiently large DPR partition was floorplanned at build time. To overcome this inefficiency, we devised an "amorphous" DPR technique that is compatible with current device and tool support but does not require the DPR partition boundaries to be a priori fixed. A collection of AFU bitstreams can be simultaneously loaded on the fabric if their footprints (the actual area used by an AFU) in the fabric do not overlap. We verified the feasibility of amorphous DPR on Xilinx Zynq System-on-Chip (SoC) FPGAs using Vivado. We evaluated the benefits of amorphous DPR in the context of a dynamically reconfigurable vision processing pipeline framework.

Motivation & Objective

• To address resource fragmentation caused by fixed DPR partition boundaries in multi-AFU FPGA systems.
• To enable dynamic, runtime co-location of diverse AFUs without prior commitment to fixed partition layouts.
• To improve fabric utilization and placement success rates in vision processing pipeline workloads.
• To reduce reconfiguration time and overhead by loading only the minimal necessary footprint area per AFU.
• To demonstrate feasibility and performance gains using Xilinx Zynq SoC FPGAs and Vivado tools.

Proposed method

• Compile multiple footprint-optimized bitstream versions for each AFU, each corresponding to a different shaped region enclosing only the AFU's actual resource usage.
• Use a static infrastructure partition with fixed AXI4 interfaces to connect AFUs, while allowing AFU footprints to be placed flexibly across the fabric.
• At runtime, select a non-overlapping combination of AFU footprints from available versions to co-locate multiple AFUs.
• Leverage existing Xilinx Vivado toolchain support for DPR while removing the need for fixed partition floorplanning at build time.
• Optimize footprint generation at build time to minimize conflicts and resource waste.
• Use runtime scheduling to select footprint configurations that maximize co-location of AFUs while avoiding overlap.

Experimental results

Research questions

• RQ1 Can amorphous DPR eliminate resource fragmentation caused by fixed DPR partition boundaries in FPGA fabrics?
• RQ2 To what extent does amorphous DPR improve the placement success rate of AFU combinations compared to standard DPR?
• RQ3 How does amorphous DPR reduce reconfiguration time and overhead compared to standard DPR with fixed partitions?
• RQ4 What is the performance impact of amorphous DPR on real-world vision processing pipeline workloads?
• RQ5 Can amorphous DPR be implemented using existing commercial FPGA tools and hardware without architectural changes?

Key findings

• Amorphous DPR significantly improves placement success rates by eliminating external and internal fragmentation, enabling more AFU combinations to coexist on the fabric.
• The average reconfiguration time for amorphous DPR is 1.1x to 1.5x lower than best-effort standard DPR, correlating directly with smaller bitstream sizes.
• Energy overhead during reconfiguration is also reduced proportionally, as it scales with bitstream size.
• The method enables dynamic, flexible sharing of FPGA resources without requiring upfront partitioning, improving effective fabric utilization.
• Evaluation on Xilinx Zynq SoC FPGAs confirms feasibility and performance gains using standard Vivado tooling.
• The approach maintains compatibility with existing AXI4 interfaces and static infrastructure, ensuring backward and forward compatibility.