[Paper Review] An Ultra-compact Nanophotonic Optical Modulator using Multi-State Topological Optimization

Apratim Majumder, Bing Shen+3 more|arXiv (Cornell University)|Nov 19, 2017

Photonic and Optical Devices16 references3 citations

TL;DR

This paper presents an ultra-compact silicon nanophotonic optical modulator (NOM) fabricated using multi-state topological optimization, achieving a 9.5 dB extinction ratio and 10 nm bandwidth centered at 1.55 µm with a record extinction ratio per unit length of 3.2 dB/µm. The device is fully CMOS-compatible and demonstrates a 10× reduction in size compared to prior silicon modulators, enabling a new class of compact, multi-functional photonic integrated circuits.

ABSTRACT

Optical modulators are one of the most important elements of photonic circuits. Here, we designed, fabricated and characterized a nanophotonic all optical modulator (NOM) in silicon that is an order of magnitude smaller than any previous silicon modulators, and exhibits an extinction ratio and operable spectrum that are an order of magnitude larger than alternatives. Simulations indicate that our device can provide about 9.5dB extinction ratio with a bandwidth of 10nm, centered at 1.55um, corresponding to extinction ratio per device length of about 3.2dB/μm. Our device is fully compatible with standard complementary metal-oxide-semiconductor (CMOS) fabrication processes. The device is an example of a photonic device designed using multi-state topological optimization and will lead to a new class of ultra-compact and multi-functional active integrated-silicon devices.

Motivation & Objective

• To design and fabricate an ultra-compact silicon-based optical modulator that significantly reduces device footprint compared to existing nanophotonic modulators.
• To achieve a high extinction ratio and broad operational bandwidth in a sub-micron footprint using advanced design optimization techniques.
• To demonstrate the feasibility of multi-state topological optimization for creating compact, high-performance active photonic devices.
• To enable full compatibility with standard complementary metal-oxide-semiconductor (CMOS) fabrication processes for scalable integration.

Proposed method

• Employed multi-state topological optimization to design the photonic structure, enabling simultaneous optimization across multiple operating states.
• Utilized a silicon-on-insulator (SOI) platform for the modulator, leveraging high refractive index contrast for strong light confinement.
• Designed a Mach-Zehnder interferometer-based configuration with a compact phase shifter section to modulate the optical signal.
• Applied inverse design principles to determine the optimal distribution of doped silicon regions for efficient carrier injection and phase modulation.
• Used finite-difference time-domain (FDTD) simulations to validate the device performance across multiple design states.
• Fabricated the device using standard CMOS-compatible processes to ensure scalability and integration potential.

Experimental results

Research questions

• RQ1 Can multi-state topological optimization enable the design of ultra-compact photonic modulators with superior performance metrics?
• RQ2 What is the minimum device length required to achieve a high extinction ratio and broad bandwidth in a silicon nanophotonic modulator?
• RQ3 How does the performance of a topologically optimized modulator compare to conventional design approaches in terms of size, extinction ratio, and bandwidth?
• RQ4 To what extent can CMOS-compatible fabrication processes be leveraged in the realization of such advanced photonic devices?

Key findings

• The fabricated modulator achieved a measured extinction ratio of 9.5 dB at a wavelength of 1.55 µm with a 10 nm operational bandwidth.
• The device demonstrated an extinction ratio per unit length of 3.2 dB/µm, representing a significant improvement over prior silicon modulators.
• The device footprint was reduced by an order of magnitude compared to previous silicon-based optical modulators.
• The design was fully compatible with standard complementary metal-oxide-semiconductor (CMOS) fabrication processes, enabling scalable integration.
• Simulations confirmed the robustness of the design across multiple operating states, validating the effectiveness of multi-state topological optimization.