[Paper Review] Complexity Analysis of Reversible Logic Synthesis

Anupam Chattopadhyay, Chander Chandak+1 more|arXiv (Cornell University)|Feb 3, 2014

Quantum Computing Algorithms and Architecture32 references12 citations

TL;DR

This paper analyzes the computational complexity of reversible logic synthesis, establishing that bounded-ancilla synthesis is NP-hard and ancilla-free synthesis is linked to cost-constrained sorting problems. It proposes a shortest-path formulation and a (0-1) ILP model, demonstrating that the shortest-path approach enables optimal synthesis for all 3-variable functions within minutes, while ILP fails to scale due to excessive runtime.

ABSTRACT

Reversible logic circuit is a necessary construction for achieving ultra low power dissipation as well as for prominent post-CMOS computing technologies such as Quantum computing. Consequently automatic synthesis of a Boolean function using elementary reversible logic gates has received significant research attention in recent times, creating the domain of reversible logic synthesis. In this paper, we study the complexity of reversible logic synthesis. The problem is separately studied for bounded-ancilla and ancilla-free optimal synthesis approaches. The computational complexity for both cases are linked to known/presumed hard problems. Finally, experiments are performed with a shortest-path based reversible logic synthesis approach and a (0-1) ILP-based formulation.

Motivation & Objective

• To analyze the computational complexity of reversible logic synthesis under bounded-ancilla and ancilla-free constraints.
• To investigate the theoretical hardness of optimal reversible circuit synthesis by linking it to known or presumed hard problems.
• To evaluate and compare two exact formulation approaches: (0-1) integer linear programming (ILP) and shortest-path-based synthesis.
• To generate comprehensive optimal results for 3-variable reversible Boolean functions using the shortest-path method.
• To identify scalability bottlenecks and future research directions for larger circuits.

Proposed method

• Models reversible logic synthesis as a shortest-path problem in a state space where nodes represent Boolean function states and edges represent reversible gate applications.
• Uses a state-space graph where each node corresponds to a truth table or ANF representation of a Boolean function, and edges correspond to gate operations (e.g., CNOT, Toffoli).
• Applies dynamic programming and pathfinding to explore all possible gate sequences from the identity function to the target function, minimizing quantum cost.
• Formulates the synthesis problem as a (0-1) integer linear program (ILP), where variables represent gate usage and constraints enforce functional correctness and gate ordering.
• Supports both positive and inverted control lines (denoted by '+' and '-' in tables), enabling flexible gate representation.
• Employs CPLEX with IntSolLim=1 to limit solution search time, though this leads to large optimality gaps for larger instances.

Experimental results

Research questions

• RQ1 Is the bounded-ancilla reversible logic synthesis problem computationally hard, and if so, to which complexity class does it belong?
• RQ2 What is the computational complexity of ancilla-free reversible logic synthesis, and how does it relate to known combinatorial problems?
• RQ3 Can the shortest-path formulation achieve optimal results for small reversible circuits (e.g., 3-variable functions) within practical time?
• RQ4 Why does the (0-1) ILP formulation fail to scale beyond small circuits despite being exact?
• RQ5 What are the trade-offs between memory-intensive exhaustive search and pathfinding-based approaches in reversible logic synthesis?

Key findings

• Bounded-ancilla reversible logic synthesis is proven to be NP-hard, linking it to known hard problems in combinatorial optimization.
• Ancilla-free reversible logic synthesis is shown to be equivalent to sorting by cost-constrained transpositions, a problem with unknown computational complexity.
• The shortest-path formulation successfully computes optimal gate counts and quantum costs for all 3-variable reversible functions in under a minute.
• For the NCTF gate family, the average quantum cost is 10.52, and the average gate count is 4.34, with all optimal values achieved.
• The (0-1) ILP formulation fails to produce optimal solutions within acceptable time, even with IntSolLim=1, due to excessive runtime and large optimality gaps.
• The shortest-path approach scales effectively to 3-variable functions but faces scalability bottlenecks for 4-variable and larger circuits due to exponential state space growth.